Abs tractBoard real estate requirements and execution speed demands ['] ,are contributing to the compressing of logic circuits to the point where test accessibility is becoming more and more difficult. The extreme of this trend is the multichip module, where accessibility at other than the 1/0 pins is inon-existent. Therefore, the testing of these devices is proving to be a difficult and tedlous problem which must be solved before commercial production of these devices can become commonplace. Through the use of a design-for-testability architecture involving boundary-scan coupled with other board-test techniques, this process can be made more manageable.
MCMCross Section Figure 1. Cross section of a multichip module showing build-up of dielectric and metallization layers and chip bonding. Substrate in this example is a multi-layer ceramic PGA. Reproduced with the permission of NCR Corporation, Cokuiibia, Soiitli Carolina.
The use of embedded test instrumentation in ASIC designs has changed dramatically over the last decade. This is due to a variety offorces that affect the semiconductor industry.Unfortunately, processes surrounding test creation and validation this instrumentation has become significantly more complicated in recent years. IEEE P1687, which is now nearing completion and ballot, addresses these issues and makes the access and control of embedded instruments nearly automatic. This poster session will illustrate the latest innovations in the standard.
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