IEEE P1687: Toward Standardized Access of Embedded Instrumentation

Posse, K.; Crouch, Alfred L.; Rearick, Jeff; Eklow, B.; Laisne, M.; Bennetts, Ben; Doege, J.; Ricchetti, Mike; Cote, J-F

doi:10.1109/test.2006.297744

Cited by 25 publications

(16 citation statements)

References 2 publications

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“…In this paper, access is defined as 1) shifting input bits into the instrument's shift register, 2) latching the contents of the shift register to be applied to the internal circuitry of the instru- The shifting out of the instrument outputs can overlap in time with shifting-in the input command bits for the next access. Considering the relatively slow P1687 clock (i.e., TCK applied to JTAG TAP) [4], [5], it is assumed that the time it takes an instrument to process the applied inputs and make the outputs ready to be captured, is less than the time it takes to move from Update-DR to Capture-DR in the TAP Controller.…”

Section: P1687 Hardwarementioning

confidence: 99%

“…Therefore, there is a need to standardize how JTAG circuitry should connect to the embedded logic. The IEEE P1687 standard proposal [2], [3], [4], [5], [6] aims to address this need of standardization by describing a flexible data transport infrastructure (called network) to interface JTAG to the chip internal instruments. P1687 has therefore received the informal name of Internal JTAG (IJTAG).…”

Section: Introductionmentioning

confidence: 99%

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Access Time Analysis for IEEE P1687

Zadegan

Ingelsson²,

Carlsson

et al. 2012

IEEE Trans. Comput.

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Abstract-The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan-chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan-path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e., concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e., network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs.

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Section: P1687 Hardwarementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Access Time Analysis for IEEE P1687

Zadegan

Ingelsson²,

Carlsson

et al. 2012

IEEE Trans. Comput.

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“…[10,15,30,36,39]. These applications have a large hardware and software infrastructure, which relies on the presence of the IEEE 1149.1 features.…”

Section: Testturnsmentioning

confidence: 99%

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

et al. 2011

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Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level.

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“…However, there is a lack of flexibility and scalability. The IEEE P1687 standard proposal [2], [3], [4], [5], [6] aims to address the need of standardization, by describing a flexible data transport infrastructure (called network) to interface JTAG to the chip internal instruments. P1687 has therefore received the informal name of Internal JTAG (IJTAG).…”

Section: Introductionmentioning

confidence: 99%

Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies

Larsson

2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Abstract:As semiconductor technologies enables highly advanced an complex integrated circuits (ICs), there is an increasing need to have more embedded design-for-test (DfT) instruments for test, debug, diagnosis, configuration, monitoring, etc. As these instruments are to be used not only at chip-level but also at board-level and system-level, a key challenge is how to access these instruments from chip terminals in a low-cost, non-intrusive, standardized, flexible and scalable manner. The well-adopted IEEE 1149.1 (Joint Test Action Group (JTAG)) standard offers lowcost, non-intrusive and standardized access but lacks flexibility and scalability, which is addressed by the on-going IEEE P1687 (Internal JTAG (IJTAG)) standardization initiative. We will discuss the need of embedded instrumentation, the shortcomings of IEEE 1149.1, the features and challenges of IEEE P1687, as well as cases studies on the usage of IEEE P1687.

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IEEE P1687: Toward Standardized Access of Embedded Instrumentation

Cited by 25 publications

References 2 publications

Access Time Analysis for IEEE P1687

Access Time Analysis for IEEE P1687

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies

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