Jagged Tiling for Intra-tile Parallelism and Fine-Grain Multithreading

Shrestha, Sunil; Manzano, Joseph; Márquez, Andrés; Feo, John; Gao, Guang R.

doi:10.1007/978-3-319-17473-0_11

Cited by 7 publications

(4 citation statements)

References 15 publications

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“…A more recent cache block sharing work, called jagged tiling, is proposed in [Shrestha et al 2014]. The polyhedral model is employed to generate code for intratile parallelization using the PLUTO framework.…”

Section: Related Work Utilizing Cache Block Sharingmentioning

confidence: 99%

Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations

Malas

Hager

Ltaief

et al. 2017

ACM Trans. Parallel Comput.

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Optimizing the performance of stencil algorithms has been the subject of intense research over the last two decades. Since many stencil schemes have low arithmetic intensity, most optimizations focus on increasing the temporal data access locality, thus reducing the data traffic through the main memory interface with the ultimate goal of decoupling from this bottleneck. There are, however, only few approaches that explicitly leverage the shared cache feature of modern multicore chips. If every thread works on its private, separate cache block, the available cache space can become too small, and sufficient temporal locality may not be achieved.We propose a flexible multi-dimensional intra-tile parallelization method for stencil algorithms on multicore CPUs with a shared outer-level cache. This method leads to a significant reduction in the required cache space without adverse effects from hardware prefetching or TLB shortage. Our Girih framework includes an auto-tuner to select optimal parameter configurations on the target hardware. We conduct performance experiments on two contemporary Intel processors and compare with the state-of-the-art stencil frameworks PLUTO and Pochoir, using four corner-case stencil schemes and a wide range of problem sizes. Girih shows substantial performance advantages and best arithmetic intensity at almost all problem sizes, especially on low-intensity stencils with variable coefficients. We study in detail the performance behavior at varying grid size using phenomenological performance modeling. Our analysis of energy consumption reveals that our method can save energy by reduced DRAM bandwidth usage even at marginal performance gain. It is thus well suited for future architectures that will be strongly challenged by the cost of data movement, be it in terms of performance or energy consumption. ACM Reference Format:Tareq M. Malas, Georg Hager, Hatem Ltaief, and David E. Keyes, 2015. Multi-dimensional intra-tile parallelization for memory-starved stencil computations. ACM Trans. Parallel Comput. 0, 0, Article 0 ( 0), 44 pages.

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Section: Related Work Utilizing Cache Block Sharingmentioning

confidence: 99%

Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations

Malas

Hager

Ltaief

et al. 2017

ACM Trans. Parallel Comput.

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“…An explicitly multi-core aware wavefront scheme leveraging the shared cache among the threads was proposed in [29] (Similar concept in exploiting parallelism within the cache block was recently performed by Shrestha et al [23]). In [29] approach the frontline update is pipelined over a group of threads sharing an outer-level cache.…”

Section: Three-dimensional 25-point Stencil With Constant Coefficientsmentioning

confidence: 99%

Multicore-Optimized Wavefront Diamond Blocking for Optimizing Stencil Updates

Malas¹,

Hager²,

Ltaief³

et al. 2015

SIAM J. Sci. Comput.

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The importance of stencil-based algorithms in computational science has focused attention on optimized parallel implementations for multilevel cache-based processors. Temporal blocking schemes leverage the large bandwidth and low latency of caches to accelerate stencil updates and approach theoretical peak performance. A key ingredient is the reduction of data traffic across slow data paths, especially the main memory interface. In this work we combine the ideas of multicore wavefront temporal blocking and diamond tiling to arrive at stencil update schemes that show large reductions in memory pressure compared to existing approaches. The resulting schemes show performance advantages in bandwidth-starved situations, which are exacerbated by the high bytes per lattice update case of variable coefficients. Our thread groups concept provides a controllable trade-off between concurrency and memory usage, shifting the pressure between the memory interface and the CPU. We present performance results on a contemporary Intel processor.

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“…Fixed sized code generation for other shapes are also tackled by many authors, such as diamond tiling [29,1], trapezoid tiling [25,8,30], hexagonal tiling [9] and etc. Recently, Shrestha [27] presented a multi-hierarchical tiling technique that explores concurrent start for the second level of tiling based on the code generation technique of Pluto. However, when tile sizes are parameterized, tiling becomes a non-linear transformation, and introduces challenges to the code generation problem.…”

Section: Tiled Code Generationmentioning

confidence: 99%

Automatic Energy Efficient Parallelization of Uniform Dependence Computations

Zou

Rajopadhye

2015

Proceedings of the 29th ACM on International Conference on Supercomputing

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Energy is now a critical concern in all aspects of computing. We address a class of programs that includes the so-called "stencil computations" that have already been optimized for speed. We target the energy expended in dynamic memory accesses, since most other components of the total energy are usually already reduced when optimizing for speed alone. For a standard shared memory multi-core processor, we seek to minimize the total number of off-chip memory accesses without sacrificing execution time. Our strategy uses two-level tiling with multiple pipelined passes. Because of the sophisticated tiling and parallelization, such codes are difficult to write by hand, especially for parametric tile sizes. They are also beyond the capability of current code generators because the schedules used are polynomial functions, more general than multidimensional schedules. We implement a parametric tiled code generator to support this strategy, and also develop a simple quantitative linear regression model for the energy consumed by a program. We experimentally validate our techniques on a set of benchmarks including those from the Polybench suite on two platforms. Our experiments show that about 78% (resp. 80%) of the dynamic memory energy consumption on an 8-core Xeon E5-2650 v2 (resp. 6-core Xeon E5-2620 v2) based machine can be avoided. This leads to a reduction in the total energy of the program by 2% to 14%.

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Jagged Tiling for Intra-tile Parallelism and Fine-Grain Multithreading

Cited by 7 publications

References 15 publications

Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations

Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations

Multicore-Optimized Wavefront Diamond Blocking for Optimizing Stencil Updates

Automatic Energy Efficient Parallelization of Uniform Dependence Computations

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