Automatic Energy Efficient Parallelization of Uniform Dependence Computations

Abstract

Energy is now a critical concern in all aspects of computing. We address a class of programs that includes the so-called "stencil computations" that have already been optimized for speed. We target the energy expended in dynamic memory accesses, since most other components of the total energy are usually already reduced when optimizing for speed alone. For a standard shared memory multi-core processor, we seek to minimize the total number of off-chip memory accesses without sacrificing execution time. Our strategy uses two-level tiling with multiple pipelined passes. Because of the sophisticated tiling and parallelization, such codes are difficult to write by hand, especially for parametric tile sizes. They are also beyond the capability of current code generators because the schedules used are polynomial functions, more general than multidimensional schedules. We implement a parametric tiled code generator to support this strategy, and also develop a simple quantitative linear regression model for the energy consumed by a program. We experimentally validate our techniques on a set of benchmarks including those from the Polybench suite on two platforms. Our experiments show that about 78% (resp. 80%) of the dynamic memory energy consumption on an 8-core Xeon E5-2650 v2 (resp. 6-core Xeon E5-2620 v2) based machine can be avoided. This leads to a reduction in the total energy of the program by 2% to 14%.

PCOT: Cache Oblivious Tiling of Polyhedral Programs

“…We also provide variability of both speed and cache behavior with respect to tile size. Some prior work on code generators for various types of tiling have empirically compared iteration space tiling and cache-oblivious methods [2,11,44,58,73]. The objective of these experiments are slightly different from ours; the main target of evaluation is the code generation tools.…”

Hybrid Static/Dynamic Schedules for Tiled Polyhedral Programs

“…Lastly, our runtime scheduling policy mandates that each processor must follow a strictly lexicographically ascending order within the block and finish all of the work within a block before being preempted. Such policy essentially guarantees a multi-pass execution of the iteration space, which was previously proven [57] to exhibit energy efficiency but was only applicable to stencil kernels.…”

“…As many authors note, such static control structures have a number of drawbacks [3,7,8,16,30,57]. First, they induce unnecessary synchronization-any tile of wavefront w must wait for all tiles of wavefront w − 1.…”

“…Third, it suffers what we call the affinity problem: data needed for a tile may not reside in that (or any) core's cache at the start of tile execution-other tiles in the previous wavefront may have evicted it. This has a cost on both time and energy, although "multipass wavefront schedules" can reduce it [57].…”