Multidimensional Intratile Parallelization for Memory-Starved Stencil Computations

Abstract

Optimizing the performance of stencil algorithms has been the subject of intense research over the last two decades. Since many stencil schemes have low arithmetic intensity, most optimizations focus on increasing the temporal data access locality, thus reducing the data traffic through the main memory interface with the ultimate goal of decoupling from this bottleneck. There are, however, only few approaches that explicitly leverage the shared cache feature of modern multicore chips. If every thread works on its private, separate cache block, the available cache space can become too small, and sufficient temporal locality may not be achieved.We propose a flexible multi-dimensional intra-tile parallelization method for stencil algorithms on multicore CPUs with a shared outer-level cache. This method leads to a significant reduction in the required cache space without adverse effects from hardware prefetching or TLB shortage. Our Girih framework includes an auto-tuner to select optimal parameter configurations on the target hardware. We conduct performance experiments on two contemporary Intel processors and compare with the state-of-the-art stencil frameworks PLUTO and Pochoir, using four corner-case stencil schemes and a wide range of problem sizes. Girih shows substantial performance advantages and best arithmetic intensity at almost all problem sizes, especially on low-intensity stencils with variable coefficients. We study in detail the performance behavior at varying grid size using phenomenological performance modeling. Our analysis of energy consumption reveals that our method can save energy by reduced DRAM bandwidth usage even at marginal performance gain. It is thus well suited for future architectures that will be strongly challenged by the cost of data movement, be it in terms of performance or energy consumption. ACM Reference Format:Tareq M. Malas, Georg Hager, Hatem Ltaief, and David E. Keyes, 2015. Multi-dimensional intra-tile parallelization for memory-starved stencil computations. ACM Trans. Parallel Comput. 0, 0, Article 0 ( 0), 44 pages.

Optimizations of Unstructured Aerodynamics Computations for Many-core Architectures

“…For example, seismic [63], stencil [64], [65], electromagnetic [66], molecular dynamics [67], Fast Multipole Methods [68], tensors [39], deep learning [69], [70], databases [49], [71], [72], big data [73], systems and graph engines [74], and many more.…”

Quasi-matrix-free Hybrid Multigrid on Dynamically Adaptive Cartesian Grids

“…Such stencil codes can, in the context of iterative solvers, significantly benefit from careful tuning such as diamond tiling. However, most tunings require invariant stencils in order to perform [37]. Our work targets problems where stencil entries are not constant.…”

Optimization of an Electromagnetics Code with Multicore Wavefront Diamond Blocking and Multi-dimensional Intra-Tile Parallelization

“…The THIIM stencil requires many bytes per grid cell, which makes it challenging to fit sufficiently large tiles in the cache memory. We have introduced a more advanced cache block sharing technique in [22], where we propose multi-dimensional intratile parallelization to achieve a further reduction in the tile size requirements and maintain architecture-friendly memory access patterns.…”

“…Our experiments require a system that allows full control over the tunable parameters of a temporally blocked stencil algorithm. The open source system provided by Malas et al [17], [22], called Girih, provides these options. Girih uses wavefront-diamond tiling with multi-dimensional intratile parallelization to construct a Multi-threaded Wavefront Diamond blocking (MWD) approach.…”

“…The staggered grid and multi-component nature of this application requires different intra-tile parallelization strategies than "standard" structured grid implementations. We use a Fixed-Execution to Data (FED) wavefront parallelization approach [22], which always assigns the same grid points to each thread while the wavefront traverses the tile. This idea maximizes the data reuse in the thread-private caches, since only boundary data instead of the full tile has to travel between threads.…”