Investigation on the Lateral Trap Distributions in Nanoscale MOSFETs During Hot Carrier Stress

Sun, Zixuan; Yu, Zhuoqing; Zhang, Zhe; Zhang, Jiayang; Wang, Runsheng; Lu, Pei-Min; Huang, Ru

doi:10.1109/led.2019.2897728

Cited by 23 publications

(10 citation statements)

References 17 publications

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“…during weak/short HC stress the impact of RTs on the aforementioned distributions is less pronounced. This is because at weak stress the MCmechanism is dominant and creates damage which is less localized compared to the typical mixture of MC-and SCmechanisms (N it can be high even near the source [33][34][35]). This scenario is very similar to variability induced by bias temperature instability, which is reduced compared to HCD variability, as we discussed in [9].…”

Section: Resultsmentioning

confidence: 99%

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Makarov

Kaczer

Chasin

et al. 2019

IEEE Electron Device Lett.

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We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hotcarrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration Nit. These deterministic densities Nit for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible.

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Section: Resultsmentioning

confidence: 99%

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Makarov

Kaczer

Chasin

et al. 2019

IEEE Electron Device Lett.

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“…The electrostatic integration (EI) of the underlap FinFET is superior, and its performance is less immune to interdevice variability and parametric fluctuations [28]. The barrier near the underlap lengths of FinFET is accentuated by spacers in the underlap FinFET as illustrated in Figure 4.…”

Section: Trigate Nanoscale Finfetmentioning

confidence: 99%

Design of Polymer-Based Trigate Nanoscale FinFET for the Implementation of Two-Stage Operational Amplifier

Suman¹,

Cheepurupalli²,

Allasi

2022

International Journal of Polymer Science

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The major motivation behind transistor scaling is the requirement for high-speed transistors with lower fabrication costs. When the fin thickness or breadth is smaller than 10 nm in a trigate FET, charges travel in a nonconfined fashion, resulting in the creation of energy subbands and causing volume inversion. In comparison to the carrier near a surface inversion layer, volume inversion experiences less interface scattering. In large-scale integrations, we have focused on developing a 3D model for surface potential by establishing the three-dimensional Poison’s equation and building a unique fin field-effect transistor (FinFET) structure. In this context, there is a growing interest in developing a low-cost, simple solution that combines plastic (polymer) as a substrate and organic materials to create electronics such as monitors and sensors. The research examines characteristics such as silicon width, oxide thickness, doping concentration, metal work-function about gate, and various surface potentials. For different circuit configurations, it also examines the DC and AC characteristics of the FinFET structure. A differential amplifier is built for RF application based on the device specifications. This work is aimed at improving the semiconductor design structure by adjusting device parameters, analyzing the results, establishing the best FinFET device preferences, and selecting an application for the optimized device. The 3D Poisson’s equation may be used to create an analytical model of a trigate nanosize FinFET, which can then be tested using a TCAD simulator. By constructing such a FinFET, we can structure and analyze various electrostatic parameters. To facilitate the creation of FinFET-based circuits, including product development, a novel transistor needs a creative device basis. The infrastructure’s support denotes a computationally advantageous numerical model that accurately depicts a FinFET. The work presents a compact model for semiconductor manufacturing that permits separate IC productions while achieving higher levels of excellence and using less power. The design outperforms the CMOS by 22.7% in gain, 31.48% in power consumption, and 12.72% in CMRR, while operating at a 5 GHz unity gain frequency.

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“…Therefore, aggressive transistor downscaling causes unavoidable reliability issues in modern integrated circuits (IC). On the one hand, among all the reliability issues, the aging effects such as bias temperature instability (BTI) [1]- [3] and hot carrier injection (HCI) [4]- [6] manifest themselves as an increase in the absolute threshold voltage (V th ) and reduction in the carrier mobility (µ), thus gradually degrading circuit performance [7], [8]. On the other hand, there are booming demand of high reliability circuits in the markets of autonomous vehicles, space operations and biomedical electronics.…”

Section: Introductionmentioning

confidence: 99%

Development and Challenges of Reliability Modeling From Transistors to Circuits

Yang

Sang

Wang

et al. 2023

IEEE J. Electron Devices Soc.

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The integration density of electronic systems is limited by the reliability of the integrated circuits. To guarantee the overall performance, the integrated circuit reliability must be modeled and analyzed at the early design stage. This paper reviews some of the most important intrinsic aging mechanisms of MOSFETs and elaborates the physical mechanism of the coupling between aging effects. Then the progress in reliability modeling under static and dynamic operational voltages is reviewed. It is found that although these models can accurately predict the degradation in short term, they are with large errors for the long-term degradation prediction. Besides, for the circuit-level reliability modeling and simulation approach, there are still problems to be solved. This article aims to provide guidance for researchers and practitioners in integrated circuit field, and highlight the challenges for reliability research. It is of great significance to the optimization of the reliability of integrated circuits.

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Investigation on the Lateral Trap Distributions in Nanoscale MOSFETs During Hot Carrier Stress

Cited by 23 publications

References 17 publications

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Design of Polymer-Based Trigate Nanoscale FinFET for the Implementation of Two-Stage Operational Amplifier

Development and Challenges of Reliability Modeling From Transistors to Circuits

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