Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket

Abstract

The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed P i -NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the P i -NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio (I ON /I OFF ) of 10 8 . Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (P i -NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive I ON /I OFF ratio of 10 8 . Moreover, the proposed P i -NT JLFET and P i -NT JAMFET exhibit an impressive I ON /I OFF ratio of ∼ 10 8 and 10 6 , respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The P i -NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the P i -NT transistor. The DMG-P i -NT transistors exhibit an enhanced I ON /I OFF ratio ∼ 10 11 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.INDEX TERMS Gate induced drain leakage (GIDL), junctionless accumulation mode FET (JAMFET), nanotube JAMFET (NT JAMFET), nanotube junctionless FET (NT JLFET), parasitic bipolar junction transistor (BJT), drain induced barrier lowering (DIBL), band-to-band tunneling (BTBT).

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

“…Extra core gate limits the scalability of Nanotube Junctionless FETs regardless of their eventual electrostatic gate control as a result, a symmetric intrinsic pocketed Pi NT JLFET with small inherent pockets at both the sides of the channel has a lower L-BTBT, resulting lateral parasitic bipolar junction transistor activity in the upcoming nanotubes. This device structure has been proposed by Jain et al 35 As observed through simulations, for a gate length of 20 nm, addition of an intrinsic pocket minimises the OFF current in the Pi-NT-JLFET by about two orders of magnitude, resulting in a significant I ON /I OFF ratio to 10 8 . The proposed Pi-Nanotube transistors architecture is superior in terms of SCEs like threshold voltage roll-off, also low drain bias sensitivity of the leakage current.…”

Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study

“…The wafer bonding is followed by the two-phase heat treatment. During first heat treatment at ~ 400-600°C, the implanted wafer A splits along the H-rich zone giving rise to an SOI wafer with an incorporated ground plane ( used [23], which is a well-established TCAD model and has been extensively used to investigate the ambipolar tunneling leakage mechanisms in TFETs [15], and lateral band-to-band-tunneling in SOI-JLFETs [5], nanowire JLFETs [24] and nanotube JLFETs [25]. Furthermore, we have not invoked any direct tunneling model to account for gate leakage through the gate dielectric in our simulations as also done in the previously reported works on SOI-JLFETs [5], [16].…”

“…We have also compared the performance of the proposed GP-JLFET with the emerging 3D-FET architectures as shown in Table II. The comparison shows that the normalized OFF-state current of the GP-JLFET and ION/IOFF ratio is relatively better compared to the emerging complex 3-D device architectures such as conventional gate all around nanowire (NW) JLFETs [24] as well as core -shell nanotube (NT) JLFETs [25] for an active silicon device layer thickness (t Si ) of 10 nm. Thus, our proposed device shows a comparatively improved OFF-state JLFET with spacers [30] 20 nm ~ 10 -10 ~10 7…”

Reduction of Random Dopant Fluctuation-induced Variation in Junctionless FinFETs via Negative Capacitance Effect

“…Investigation also reports that JL-FETs are more sensitive to RDF than IM-FETs in baseline doping levels in silicon-bulk channel [15]. In rencent years, many novel junctionless architectures have been published in reputed journals, like Nanowire junctionless FETs and Nano tube junctionless FETs [16][17]. Therefore, electrical properties variability of conventional JL-FETs induced by RDF is going to be a worthwhile concern when the device scales to the nanometer region with the total number of dopant atoms increasingly discretized.…”