The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed P i -NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the P i -NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio (I ON /I OFF ) of 10 8 . Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (P i -NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive I ON /I OFF ratio of 10 8 . Moreover, the proposed P i -NT JLFET and P i -NT JAMFET exhibit an impressive I ON /I OFF ratio of ∼ 10 8 and 10 6 , respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The P i -NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the P i -NT transistor. The DMG-P i -NT transistors exhibit an enhanced I ON /I OFF ratio ∼ 10 11 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.INDEX TERMS Gate induced drain leakage (GIDL), junctionless accumulation mode FET (JAMFET), nanotube JAMFET (NT JAMFET), nanotube junctionless FET (NT JLFET), parasitic bipolar junction transistor (BJT), drain induced barrier lowering (DIBL), band-to-band tunneling (BTBT).
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.