Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO&lt;sub&gt;2&lt;/sub&gt; VS Si-cap

Mitard, J.; Bellenger, Florence; Witters, L.; Jaeger, B. De; Vincent, Benjamin; Nyns, L.; Martens, Koen; Vrancken, Evi; Wang, G.; Lin, Dennis; Loo, Roger; Caymax, M.; Meyer, K. De; Heyns, Marc; Horiguchi, N.

doi:10.7567/ssdm.2011.e-1-1

Cited by 4 publications

(5 citation statements)

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“…A stronger correlation in the latter case is noted. Severe charge trapping might induce incorrect split-CV mobility extraction as suggested in [15]. Tinv.…”

Section: Figmentioning

confidence: 96%

Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO<inf>2</inf>/HfO<inf>2</inf> pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Franco

Kaczer

Roussel

et al. 2013

2013 IEEE International Electron Devices Meeting

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We study charge trapping in a variety of Ge-based pMOS and nMOS technologies, either with Si passivation and conventional SiO 2 /HfO 2 gate stack, or with GeO x /high-k gate stacks. A general model for understanding this phenomenon in alternative substrate/dielectric systems is proposed. We discuss two different approaches to pursue a reduction of charge trapping in alternative material systems, which will be necessary for achieving reliable high-mobility devices.

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“…A stronger correlation in the latter case is noted. Severe charge trapping might induce incorrect split-CV mobility extraction as suggested in [15]. Tinv.…”

Section: Figmentioning

confidence: 96%

Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO<inf>2</inf>/HfO<inf>2</inf> pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Franco

Kaczer

Roussel

et al. 2013

2013 IEEE International Electron Devices Meeting

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“…The electric field over the interfacial GeO 2 layer was calculated from E ox = (V g − V th ) × 3.9/(6× EOT), where EOT is the SiO 2 equivalent thickness, and the GeO 2 has a dielectric constant of six [29].…”

Section: Devices and Experimentsmentioning

confidence: 99%

“…It has been reported that the interface state density rises substantially toward the band edge, so that an assumption of uniform energy distribution can underestimate the contribution of D it . As a second-order approximation, we use the energy profile reported in [29] for D it . As shown in Fig.…”

Section: Contribution Of Generated Interface Statesmentioning

confidence: 99%

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Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With <inline-formula> <tex-math notation="TeX">${\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Stack

Zhang

et al. 2014

IEEE Trans. Electron Devices

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Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO 2 /Al 2 O 3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge-and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional V g -accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO 2 /Al 2 O 3 can be fully annealed at 150°C; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., E v , when neutral, lift well above E v after charging, and return below E v following neutralization.Index Terms-Al 2 O 3 , degradations, Ge MOSFETs, Ge/GeO 2 , high-k on Ge, hole traps, lifetime, negative-bias temperature instability (NBTI), positive charges (PCs).

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“…In this work, fast pulse measurement time is t m =5 µs to minimize the recovery. Temperature is either RT or 125 o C. The electric field over the interfacial GeO 2 layer was calculated from Eox=(Vg-Vth) ×3.9/(6×EOT), where EOT is the SiO 2 capacitance equivalent thickness and the GeO 2 has a dielectric constant of 6 [20].…”

Section: Devices and Experimentsmentioning

confidence: 99%

A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO₂/Ge and SiON/Si pMOSFETs

Zhang

et al. 2016

IEEE Trans. Electron Devices

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Abstract-High mobility germanium (Ge) channel is considered as a strong candidate for replacing the Si in pMOSFETs in near future. It has been reported that the conventional power-law degradation kinetics of Si devices is inapplicable to Ge. In this work, further investigation is carried out on defect energy distribution, which clearly shows that this is because the defects in GeO 2 /Ge and SiON/Si devices have different physical properties. Three main differences are: 1) Energy alternating defects (EAD) exist in Ge devices but insignificant in Si; 2) The distribution of as-grown hole traps (AHT) has a tail in the Ge band gap but not in Si, which plays an important role in degradation kinetics and device lifetime prediction; 3) EAD generation in Ge devices requires the injected charge carriers to overcome a 2 nd energy barrier, but not in Si. Taking the above differences into account, the power law kinetics of EAD generation can be successfully restored by following a new procedure, which can assist in the Ge process/device optimization.

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Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO<sub>2</sub> VS Si-cap

Cited by 4 publications

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Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO<inf>2</inf>/HfO<inf>2</inf> pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO<inf>2</inf>/HfO<inf>2</inf> pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With <inline-formula> <tex-math notation="TeX">${\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Stack

A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO₂/Ge and SiON/Si pMOSFETs

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Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO<sub>2</sub> VS Si-cap

Cited by 4 publications

References 0 publications

Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO<inf>2</inf>/HfO<inf>2</inf> pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO<inf>2</inf>/HfO<inf>2</inf> pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With <inline-formula> <tex-math notation="TeX">${\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Stack

A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO2/Ge and SiON/Si pMOSFETs

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A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO₂/Ge and SiON/Si pMOSFETs