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This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large vertical compressive strain is observed in metal gate FinFETs, and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFET lateral interfaces with respect to (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of stress components in the fin width, height, and length directions on the mobility of both n- and p-type FinFETs and to identify optimal stress configurations. Finally, self-consistent Monte Carlo simulations are used to investigate how the most favorable stress configurations can improve the on current of nanoscale MOSFETs

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A 200GHz F, SiGe:C HBT has been integrated into a 0.13pm BiCMOS technology. A previous generation low complexity quasi selfaligned arcbiteeture (QSA) is scaled down both in a lateral and vertical way. Lateral suing is obtained by using present-day step and scan tools. Vertical sizing is achieved by reducing the thermal budget of the active module and by an aggressive scaling of the SiGe:C base epitaxial Layer. A deep trench module featuring a thick oxide Liner has been developed. Excellent DC parameters and peak FUFmax values of 200/160GHz are demonstrated. The CMOS device characteristics remain unchanged by applying low thermal budget processing in the bipolar module.