8&amp;#x00C5; T&lt;inf&gt;inv&lt;/inf&gt; gate-first dual channel technology achieving low-V&lt;inf&gt;t&lt;/inf&gt; high performance CMOS

Witters, L.; Takeoka, Shinji; Yamaguchi, S.; Hikavyy, Andriy; Shamiryan, Denis; Cho, M.; Chiarella, T.; Ragnarsson, L.-Å.; Loo, Roger; Kerner, C.; Crabbe, Y.; Franco, J.; Tseng, Joshua; Wang, W.E.; Röhr, E.; Schram, T.; Richard, Olivier; Bender, Hugo; Biesemans, S.; Absil, P.; Hoffmann, T.

doi:10.1109/vlsit.2010.5556219

Cited by 28 publications

(17 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In line with prior studies (1)(2)(3), pFETs with biaxially strained SiGe channels feature lower hysteresis under NBTI stress than Si channel control devices at the same T inv (Fig. 6).…”

Section: Hole Mobilitysupporting

confidence: 91%

Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability

Frank¹,

Cartier²,

Ando³

et al. 2013

ECS Trans.

View full text Add to dashboard Cite

We demonstrate that aggressive gate dielectric scaling in hafniumbased high-k/metal gate (HKMG) p-channel metal-oxidesemiconductor field-effect transistors (pFETs) with biaxially strained silicon germanium (SiGe) channels can be achieved in gate-first integration via remote interfacial SiO 2 scavenging by metal-doped titanium nitride gates. We show that an inversion thickness (T inv ) of 0.86 nm can be reached, corresponding to an equivalent oxide thickness (EOT) of about 0.45-0.5 nm. We then provide a detailed study of interlayer-scaling-induced pFET threshold voltage increase and hole mobility reduction, and we establish an exponential interlayer thickness dependence of negative bias temperature instability (NBTI), resulting in shrinking reliability margins that will require gate stack optimization or reduced operating voltage. Previously shown to be effective for nFETs, our results demonstrate that remote oxygen scavenging is an attractive scaling option for dual-channel CMOS.

show abstract

“…In line with prior studies (1)(2)(3), pFETs with biaxially strained SiGe channels feature lower hysteresis under NBTI stress than Si channel control devices at the same T inv (Fig. 6).…”

Section: Hole Mobilitysupporting

confidence: 91%

Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability

Frank¹,

Cartier²,

Ando³

et al. 2013

ECS Trans.

View full text Add to dashboard Cite

show abstract

“…Although several groups have already demonstrated functional Si devices with aggressively scaled EOT down to ∼ 5 Å [1], [2], the stability of their parameters at operating conditions cannot be guaranteed [3], [4]. Meanwhile, the use of high-mobility channels is being considered for further device performance enhancement in future CMOS technology nodes [5], [6]. The SiGe or Ge channel quantumwell (QW) technology ( Fig.…”

Section: Introductionmentioning

confidence: 99%

“…While the interface passivation of non-Si channel materials is typically considered a challenging and critical issue, extremely promising device performance was recently obtained by growing epitaxially a thin Si passivation layer (Si cap) on top of a pMOS (Si)Ge channel [5], [9]. This approach allows also for the use of a standard high-k/metal gate stack consisting of a SiO 2 interfacial layer grown by oxidation of the Si cap and a HfO 2 layer.…”

Section: Introductionmentioning

confidence: 99%

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Franco

Kaczer

Mitard

et al. 2013

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a SiO 2 /HfO 2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups.

show abstract

“…The physical thickness of HfO 2 and ZrO 2 are 1.8 nm. The EOT is determined by a high-frequency (up to 20 MHz) C-V technique, as the high leakage current in sub-1-nanometer devices makes it difficult to detect clear maximum capacitance with the conventional C-V technique [11]. The electric field is calculated by considering the inversion thickness (T inv ) that is extracted from the high-frequency C-V. NBTI measurements are performed on W × L = 10 × 1-μm 2 MOSFETS at 125°C.…”

Section: Introductionmentioning

confidence: 99%

Improved NBTI reliability with sub-1-nanometer EOT ZrO₂ gate dielectric compared with HfO₂

Cho

Kaczer

Kauerauf

et al. 2013

IEEE Electron Device Lett.

View full text Add to dashboard Cite

The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO 2 and HfO 2 dielectrics with metal gate is investigated. The threshold voltage shift ( V TH ) at identical NBTI overdrive stress conditions is observed to be lower in ZrO 2 than in HfO 2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation ( N it ) in the sub-1-nanometer EOT devices, with ZrO 2 devices showing about one order of magnitude lower N it than HfO 2 device. However, the N it contribution to the total V TH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO 2 , which decisively reduces NBTI in ZrO 2 gate dielectric.Index Terms-Dielectric reliability, negative bias temperature instability (NBTI), oxide defect, thin equivalent oxide thickness (EOT).

show abstract

8Å T<inf>inv</inf> gate-first dual channel technology achieving low-V<inf>t</inf> high performance CMOS

Cited by 28 publications

References 1 publication

Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability

Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Improved NBTI reliability with sub-1-nanometer EOT ZrO₂ gate dielectric compared with HfO₂

Contact Info

Product

Resources

About

8&#x00C5; T<inf>inv</inf> gate-first dual channel technology achieving low-V<inf>t</inf> high performance CMOS

Cited by 28 publications

References 1 publication

Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability

Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Improved NBTI reliability with sub-1-nanometer EOT ZrO2 gate dielectric compared with HfO2

Contact Info

Product

Resources

About

8Å T<inf>inv</inf> gate-first dual channel technology achieving low-V<inf>t</inf> high performance CMOS

Improved NBTI reliability with sub-1-nanometer EOT ZrO₂ gate dielectric compared with HfO₂