Investigation of novel solder patterns for power delivery and heat removal support

Brunschwiler, Thomas; Madhour, Yassir; Tick, T.; Schlottig, Gerd; Oggioni, Stefano

doi:10.1109/ectc.2013.6575605

Cited by 7 publications

(5 citation statements)

References 20 publications

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“…Squares and circles indicate respectively dome-shaped rings and rings with balling. From these results, a close to constant critical aspect ratio of approximately 0.65 can be extracted, similar to the one established for thicker solder structures in [16], thus adding to the range of experimented deposited solder heights. Structures 4A to 4D behaved similarly.…”

Section: B Reflow Testssupporting

confidence: 74%

“…Structures 4A to 4D behaved similarly. Brunschwiler et al [16] showed that for long solder rails an invariant critical aspect ratio for different rail widths could be explained theoretically without the influence of gravitational forces (Bond numbers below one). In that case the minimal energy state was equivalent to the geometry with the minimal Fig.…”

Section: B Reflow Testsmentioning

confidence: 99%

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Integration of intra chip stack fluidic cooling using thin-layer solder bonding

Madhour

Zervas

Schlottig

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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Abstract-Three-dimensional (3D) stacking of integratedcircuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. Thus, the development of new chip cooling concepts is of utmost importance. Therefore, scalable cooling solutions for chip stacks, such as interlayer cooling, need to be investigated. This paper presents a new concept for the integration of intra chip stack fluidic cooling, namely die-embedded microchannels for single-and twophase thermal management, using a patterned thin-layer eutectic solder bonding technique for the stack assembly. Results showed the successful fabrication of 5-layer chip stacks with embedded microchannels and high aspect ratio TSVs. Optical inspections demonstrated the proper bond line formation and direct current (DC) daisy-chain electrical tests indicated the successful combination of TSVs with thin-layer solder interconnects. Mechanical shear tests on die-on-die bonded samples showed the strength of the patterned thin-layer solder bond (16MPa). An added solder ring-pad component to seal the electrically active pad from any conductive liquid coolant was also investigated and reflow tests on such geometries showed the appearance of a balling effect along the solder ring line. This balling was found to be mitigated when the ring aspect ratio (deposited solder height to ring width ratio) was kept below the experimentally observed critical value of 0.65.

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Section: B Reflow Testssupporting

confidence: 74%

Section: B Reflow Testsmentioning

confidence: 99%

Integration of intra chip stack fluidic cooling using thin-layer solder bonding

Madhour

Zervas

Schlottig

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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“…The thermal characterization of the solder interface required specific specimens. Two silicon dies of known thickness were joined with either an array of solder balls, the Rail1 or the Rail2 pattern [10]. The resulting bond-line height and the initial solder height after deposition and reflow are reported in Table 3.…”

Section: Effective Thermal Resistancementioning

confidence: 99%

“…The effective thermal resistance characterization of the TPP laminates was performed with a self-made bulk thermal tester [10]. The laminates are cut into specimens 10×10mm 2 .…”

Section: Effective Thermal Resistancementioning

confidence: 99%

Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Implementation

Brunschwiler

Tick

Castriotta

et al. 2014

Proceedings of the 5th Electronics System-Integration Technology Conference (ESTC)

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We report on the design, implementation and performance of a laminate named Thermal Power Plane and solder joints that enable dual-side electrical interconnects (EIC) to a chip stack. This novel packaging topology with a laminate on both sides of the chip stack doubles the number of EIC thus supporting increased communication bandwidth and power density. In addition, in a two-die stack, all power TSVs can be eliminated with the advantage of gained silicon active area. The use of two laminates also enables individual test & burnin of the dies before stack formation.The TPP needs to provide efficient heat removal and current feed in the out-of-plane and in-plane direction, respectively. An 8+1 core-less build-up laminate with aligned and stacked thermal laminate vias (TLVs) was designed and implemented. Bar-, chevron-and mesh-like copper planes with varying TLV densities were characterized. The mesh design resulted in minimal warpage and voltage drop. The bar and chevron designs result in the lowest thermal resistance. In combination with rail-shaped solder interconnects interfacing between TPP and top chip, the overall thermal resistance of the junction to cold plate of the dual-side EIC approach can outperform that of the standard single-side EIC package. The electrical DC characteristics of the TPP was also evaluated experimentally. The sheet resistance of 0.21 mΩ allows the supply of the required currents within the voltage uniformity requirements. In general, the experimental evaluation supports the feasibility of the proposed dual-side EIC concept supporting further performance and efficiency scaling of highperformance chip stacks.

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“…A careful design of the sealing ring is required to prevent local solder accumulation, referred to as "balling" (Fig. 6b), which can potentially result in electrical shorts (20,21). Sealing rings can be omitted when using dielectric refrigerants as done in two-phase cooling.…”

Section: Dual-side Coolingmentioning

confidence: 99%

(Invited) Wafer-Level Integration of Embedded Cooling Approaches

Paredes¹,

Madhour²,

Schlottig³

et al. 2014

ECS Trans.

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New thermal management solutions to keep components within thermal limits are needed to fully exploit the potential of 3D integration of ICs yielding dense electronic systems with increased performance and power efficiency. A roadmap from embedded single-side towards 3D interlayer cooling is presented. The characteristics of single-phase water and two-phase dielectric cooling are discussed further. Dual-side cooling was identified as an intermediate step considering an active cooled interposer combining thermal and electrical functionality. Finally, various design aspects for interlayer cooling in 3D chip stacks are listed that can leverage wafer-level bonding as cost-efficient implementation of such cooling concepts.

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Investigation of novel solder patterns for power delivery and heat removal support

Cited by 7 publications

References 20 publications

Integration of intra chip stack fluidic cooling using thin-layer solder bonding

Integration of intra chip stack fluidic cooling using thin-layer solder bonding

Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Implementation

(Invited) Wafer-Level Integration of Embedded Cooling Approaches

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