The heat-removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters <= 200 mu m. An experimental investigation with uniform and double-side heat flux at Reynolds numbers <= 1,000 and heat transfer areas of 1 cm(2) was carried out to identify the most efficient interlayer heat-removal structure. The following structures were tested: parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mu m and fluid structure heights of 100-200 mu m. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin in-line structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks having a 4-cm(2) heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from > 200 W/cm(2) at 1 cm(2) and > 50 mu m interconnect pitch to < 100 W/cm(2) at 4 cm(2). From experimental data, friction factor and Nusselt number correlations were derived for pin fin in-line and staggered structures

Non-isothermal liquid evaporation in micro-pore structures is studied experimentally and numerically using the lattice Boltzmann method. A hybrid thermal entropic multiple-relaxation-time multiphase lattice Boltzmann model (T-EMRT-MP LBM) is implemented and validated with experiments of droplet evaporation on a heated hydrophobic substrate. Then liquid evaporation is investigated in two specific pore structures, i.e. spiral-shaped and gradient-shaped micro-pillar cavities, referred to as SMS and GMS, respectively. In SMS, the liquid receding front follows the spiral pattern; while in GMS, the receding front moves layer by layer from the pillar rows with large pitch to the rows with small one. Both simulations agree well with experiments. Moreover, evaporative cooling effects in liquid and vapour are observed and explained with simulation results. Quantitatively, in both SMS and GMS, the change of liquid mass with time coincides with experimental measurements. The evaporation rate generally decreases slightly with time mainly because of the reduction of liquid–vapour interface. Isolated liquid films in SMS increase the evaporation rate temporarily resulting in local peaks in evaporation rate. Reynolds and capillary numbers show that the liquid internal flow is laminar and that the capillary forces are dominant resulting in menisci pinned to the pillars. Similar Péclet number is found in simulations and experiments, indicating a diffusive type of heat, liquid and vapour transport. Our numerical and experimental studies indicate a method for controlling liquid evaporation paths in micro-pore structures and maintaining high evaporation rate by specific geometry designs.

Organic light-emitting diodes with ferromagnetic contacts are fabricated, and their emission intensity is studied at room temperature for parallel and antiparallel magnetization configuration of anode and cathode. Sweeping the magnetic field applied parallel to the electrode allows the magnetization of the two electrodes to be switched independently. The electroluminescence intensity for the antiparallel magnetic configuration is found to be enhanced as compared to the parallel one. We show that this increase is not evidence of spin injection but is a consequence of the magnetic-field dependence of the electroluminescence intensity combined with magnetic stray fields from the electrodes.

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Abstract-Liquid-cooling using microchannel heat sinks etched on silicon dies is seen as a promising solution to the rising heat fluxes in two-dimensional and stacked three-dimensional integrated circuits. Development of such devices requires accurate and fast thermal simulators suitable for early-stage design. To this end, we present 3D-ICE, a compact transient thermal model (CTTM), for liquid-cooled ICs. 3D-ICE was first advanced incorporating the 4-resistor model-based CTTM (4RM-based CTTM). Later, it was enhanced to speed up simulations and to include complex heat sink geometries such as pin fins using the new 2 resistor model (2RM-based CTTM). In this paper, we extend the 3D-ICE model to include liquid-cooled ICs with multi-port cavities, i.e., cavities with more than one inlet and one outlet ports, and non-straight microchannels. Simulation studies using a realistic 3D multiprocessor system-on-chip (MPSoC) with a 4-port microchannel cavity highlight the impact of using 4-port cavity on temperature and also demonstrate the superior performance of 2RM-based CTTM compared to 4RM-based CTTM. We also present an extensive review of existing literature and the derivation of the 3D-ICE model, creating a comprehensive study of liquid-cooled ICs and their thermal simulation from the perspective of computer systems design. Finally, the accuracy of 3D-ICE has been evaluated against measurements from a real liquid-cooled 3D-IC, which is the first such validation of a simulator of this genre. Results show strong agreement (average error < ), demonstrating that 3D-ICE is an effective tool for early-stage thermal-aware design of liquid-cooled 2D-/3D-ICs.

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We address integration density in future computers based on packaging and architectural concepts of the human brain: a dense 3-D architecture for interconnects, fluid cooling, and power delivery of energetic chemical compounds transported in the same fluid with little power needed for pumping. Several efforts have demonstrated that by vertical integration, memory proximity and bandwidth are improved using efficient communication with low-complexity 2-D arrays. However, power delivery and cooling do not allow integration of multiple layers with dense logic elements. Interlayer cooled 3-D chip stacks solve the cooling bottlenecks, thereby allowing stacking of several such stacks, but are still limited by power delivery and communication. Electrochemical power delivery eliminates the electrical power supply network, freeing valuable space for communication, and allows scaling of chip stacks to larger systems beyond exascale device count and performance. We find that historical efficiency trends are related to density and that current transistors are small enough for zetascale systems once communication and supply networks are simultaneously optimized. We infer that biological efficiencies for information processing can be reached by 2060 with ultracompact space-filled systems that make use of brain-inspired packaging and allometric scaling laws.