2011
DOI: 10.1147/jrd.2011.2165677
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Toward five-dimensional scaling: How density improves efficiency in future computers

Abstract: We address integration density in future computers based on packaging and architectural concepts of the human brain: a dense 3-D architecture for interconnects, fluid cooling, and power delivery of energetic chemical compounds transported in the same fluid with little power needed for pumping. Several efforts have demonstrated that by vertical integration, memory proximity and bandwidth are improved using efficient communication with low-complexity 2-D arrays. However, power delivery and cooling do not allow i… Show more

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Cited by 71 publications
(37 citation statements)
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“…As the power of the cell scales linearly with the area of the co-laminar interface, these low profile (low channel height) cells have also been restricted in their individual performance to low power operation ( < 100 mW). If these challenges can be overcome it has been suggested that 'on-chip' power and 9 cooling of microprocessors may become an attractive option for this technology [124], [125].…”
Section: Research Perspectivesmentioning
confidence: 99%
“…As the power of the cell scales linearly with the area of the co-laminar interface, these low profile (low channel height) cells have also been restricted in their individual performance to low power operation ( < 100 mW). If these challenges can be overcome it has been suggested that 'on-chip' power and 9 cooling of microprocessors may become an attractive option for this technology [124], [125].…”
Section: Research Perspectivesmentioning
confidence: 99%
“…All of this suggests to Michel that, if computers are going to be packaged three-dimensionally, it would be worthwhile to try to emulate the brain's hierarchical architecture 6 . Such a hierarchy is already implicit in some proposed 3D designs: stacks of individual microprocessor chips (on which the transistors themselves could be wired in a branching network) are stacked into towers and interconnected on circuit boards, and these, in turn, are stacked together, enabling vertical communication between them.…”
Section: Smart Buildmentioning
confidence: 99%
“…T HREE dimensional stacking of multiprocessor system-onchips (3D MPSoCs), integrated using high-speed through-silicon vias (TSVs), possesses immense potential in accelerating the computational power of high performance servers and datacenters of the future [4]. But this vertical integration of CMOS circuits in the long-term is impeded by the inability of the current air-cooled heat sinks in handling rising heat fluxes [5].…”
Section: Introductionmentioning
confidence: 99%