Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m K and 2.8 W/m K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry versus wet filling of filler particles, the optimal bimodal nanosuspension formulation and matrix material feed, and the over-pressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 1500 thermal cycles, as well as to a two-die chip stack. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8 - or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-artcapillary thermal underfill.
Abstract-Three-dimensional (3D) stacking of integratedcircuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. Thus, the development of new chip cooling concepts is of utmost importance. Therefore, scalable cooling solutions for chip stacks, such as interlayer cooling, need to be investigated. This paper presents a new concept for the integration of intra chip stack fluidic cooling, namely die-embedded microchannels for single-and twophase thermal management, using a patterned thin-layer eutectic solder bonding technique for the stack assembly. Results showed the successful fabrication of 5-layer chip stacks with embedded microchannels and high aspect ratio TSVs. Optical inspections demonstrated the proper bond line formation and direct current (DC) daisy-chain electrical tests indicated the successful combination of TSVs with thin-layer solder interconnects. Mechanical shear tests on die-on-die bonded samples showed the strength of the patterned thin-layer solder bond (16MPa). An added solder ring-pad component to seal the electrically active pad from any conductive liquid coolant was also investigated and reflow tests on such geometries showed the appearance of a balling effect along the solder ring line. This balling was found to be mitigated when the ring aspect ratio (deposited solder height to ring width ratio) was kept below the experimentally observed critical value of 0.65.
The present study deals with experimental investigation of the delamination toughness of EMC (epoxy molding compound) and Copper-leadframe interfaces. Test samples were directly obtained from the production line. EMC is attached on copper substrates with various surface treatments. Mixed mode bending experiments were performed under various temperature and moisture environments. The test procedure and some results were reported previously in ECTC08 and ECTC09 [1–2]. Recently, we studied the effect of delaminated surfaces in order to get better understanding of the established fracture toughness. Therefore, after the delamination experiments, some of the delaminated samples were subjected to various surface analyses (SEM, FIB, EDX). Two types of failure patterns are found depending on the loading mode mixture, and the environmental conditions. Firstly, depending on the type of copper surface treatment, pure interface delamination is observed for some of the interfaces. Here, we observed clean delaminated copper surfaces. The second type of failure is a combination of interface delamination and compound cracking. Here, it is found that after the separation of interfaces, some EMC remains on the copper surface. In this case the experiment results showed that the interface delamination and molding compound cracking combined failure occurs at relatively high force values
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