Abstract:We report on the design, implementation and performance of a laminate named Thermal Power Plane and solder joints that enable dual-side electrical interconnects (EIC) to a chip stack. This novel packaging topology with a laminate on both sides of the chip stack doubles the number of EIC thus supporting increased communication bandwidth and power density. In addition, in a two-die stack, all power TSVs can be eliminated with the advantage of gained silicon active area. The use of two laminates also enables indi… Show more
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