Investigation of dielectric pocket induced variations in tunnel field effect transistor

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

“…The increase in leakage current observed with a rise in ITC density in the proposed structure 2 is due to the increase in E x [40,41], as seen in figures 11(a)-(c). A higher E x causes reliability issues such as ITC generation and leakage current, which degrade the device performance.…”

Investigating linearity and effect of temperature variation on analog/RF performance of dielectric pocket high-k double gate-all-around (DP-DGAA) MOSFETs

“…But, the presence of dielectric pocket in MOSFET mitigates the drain current and transconductance (g m ) in contrast to bulk MOSFET because of the larger effective channel length [18][19][20]. A number of researchers have attempted the successful execution of DP technology in various classical (single-gate) and multi-gate MOS structures [20][21][22][23][24][25][26][27][28]. The literature, however, is replete with the details of the induction of DP technology in doublegate (DG) FETs [23][24][25][26][27][28].…”