Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET

Rathore, Sunil; Jaisawal, Rajeewa Kumar; Kondekar, P. N.; Bagga, Navjeet

doi:10.1016/j.mejo.2023.105904

Cited by 3 publications

(2 citation statements)

References 17 publications

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“…The static noise margin of GNRFET is more at various W/L ratio compared to CMOS based SRAM circuit [23]. The RF/analog and linearity behaviour of Nanosheet FET is reported by with and without considering the self-heating effect for wide variation in ambient temperatures [24]. The performance of various combinational circuits including logic gates and adder are evaluated using Graphene based nanoribbon FET [25].…”

Section: Introductionmentioning

confidence: 99%

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Rai,

Sharma,

Saha

et al. 2024

Phys. Scr.

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In this work, the trap sensitivity of single material gate (SMG) and dual material gate (DMG) nano ribbon FETs (NRFETs) are reported using TCAD Sentaurus Device simulator. The trap sensitivity is extracted for Gaussian trap distribution of both acceptor and donor type traps. We have reported the trap sensitivity for the variation in trap concentration, energy peak position, work function of metal gate, and temperature for both the NRFETs. It is realized that trap sensitivity is greater and lesser than 100% for acceptor type trap in SMG and DMG NRFETs, respectively, whereas, such sensitivity is 147% and 123% for donor type trap concentration, respectively. Temperature also shows a significant variation in trap sensitivity for both the NRFETs. The increase in work function leads to the reduction in trap sensitivity for both NRFETs in existence of acceptor and donor trap charges. The maximum sensitivity in trap are 400% and 275% for SMG and DMG NRFETs, respectively, in presence of donor trap concentration. Moreover, the trap sensitivity is very insignificant at high gate bias for donor type trap concentration with wide variation in parameters.

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Section: Introductionmentioning

confidence: 99%

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Rai,

Sharma,

Saha

et al. 2024

Phys. Scr.

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“…Jegadheesan et al [21] proposed a super steep retrograde silicon substrate to suppress the self-heating in SNSHFETs. Rathore et al [15], [22] investigated analog/RF and linearity performance of nanosheet FET and proposed diamond-like-carbon which has higher thermal conductivity, in place of SiO 2 to improve the thermal reliability of silicon-on-insulator structures. Tsen et al [23] proposed inter-bridges between stacked channels to improve the device heat dissipation and reduce temperature difference among the channels of treeFET.…”

mentioning

confidence: 99%

Impact of Device-to-Device Thermal Interference Due to Self-Heating on the Performance of Stacked Nanosheet FETs

Balasubbareddy,

Sivasankaran

2024

IEEE Access

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The stacked nanosheet field effect transistor (SNSHFET) exhibits superior electrostatic performance with its increased effective channel width. However, as the technology node progressing towards angstrom dimensions, self-heating became one of the major challenges in SNSHFETs due to their confined geometry. The self-heating impacts not only the respective device, but also its contiguous device on the same substrate. In this paper, the thermal impact of heat stacked nanosheet FET (He-FET) on proximal cool stacked nanosheet FET (Co-FET) is studied at 7 nm technology node. Thermal impact on DC and analog/RF performance of Co-FET is deliberated by varying the inter-device spacing (IDS) and shallow trench isolation (STI) depth between the two stacked nanosheet FETs. It has been observed that, self-heating induced thermal energy of He-FET shows more impact on the bottom channels compared to the top channels in the Co-FET. The electron mobility is reduced by 4.25% in the channel near to the substrate compared to the channel near to contacts. The transit frequency (f T ) and the maximum oscillation frequency (f max ) of 131.5 GHz and 435 GHz were obtained, respectively with the optimization of IDS of 30 nm and STI depth of 50 nm. INDEX TERMSInter-device spacing, Self-heating, Shallow trench isolation depth, Stacked nanosheet FET, Thermal intrude.

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Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes

Kallepelli,

Maheshwaram,

Vadthiya

2023

Microelectronics Journal

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Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET

Cited by 3 publications

References 17 publications

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Impact of Device-to-Device Thermal Interference Due to Self-Heating on the Performance of Stacked Nanosheet FETs

Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes

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