Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes

Kallepelli, Sagar; Maheshwaram, Satish; Vadthiya, Narendar

doi:10.1016/j.mejo.2023.105986

Cited by 1 publication

(1 citation statement)

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“…With ever-increasing short-channel effect [5][6][7][8] as a consequence of down-sizing, requirements of novel materials, topologies, and technologies are generated. DG MOSFET is the first solution proposed and established [9,10] primarily as a suitable alternative, capable of working in both symmetric and asymmetric modes [11][12][13][14][15][16][17], with each providing unique benefits based on specific needs. In traditional DG MOSFETs, independent gate operation is utilized to enhance performance of devices, diminish V th -roll-off, and improve DIBL to suppress SCEs.…”

Section: Introductionmentioning

confidence: 99%

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Basak,

Deyasi,

Sarkar

2024

Phys. Scr.

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Impact of underlap layer is analytically investigated on asymmetric junctionless dual material double gate MOSFET (AJDMDG) to reduce subthreshold slope and threshold voltage, which are two essential requirements with shrinking device dimensions to avoid short channel effects. The model utilizes two-dimensional Poisson’s equation with parabolic approximation for determining electrical parameters where dimensional ranges are kept within fabrication limit. Excellent accuracy is found for the obtained analytical outcome, when compared with results obtained from TCAD ATLAS simulator. Comparative study is extended for conventional junctionless DMDG (JDMDG) and underlap asymmetric junctionless single material DGFET (UAJDG) device, having identical dimensional parameters and biasing ranges; where the present structure exhibits superior performance in terms of threshold voltage, subthreshold slope and DIBL of 34.57%, 62.85% and 69.85% respectively compared to JDMDG and 12.50%, 26.08% and 40.25% respectively w.r.t UAJDG structure. Supremacy of the proposed architecture is further established with RF/analog Fig.ures of Merit (FOMs), which are essential for designing low power analog amplifier.

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