Investigation and Analysis of Mismatching Properties for Nanoscale Strained MOSFETs

Abstract

This paper investigates and analyzes the matching properties of nanoscale strained MOSFETs under various bias conditions. Through a comprehensive comparison between coprocessed strained and unstrained PMOSFETs, the impact of processinduced uniaxial strain on the matching performance of MOS devices has been assessed and analyzed. Our examination indicates that, in the low-gate-voltage-overdrive (|V gst |) regime, the normalized drain current mismatch (σ(∆I d )/I d ) of the strained device is almost the same as that of the unstrained one at a given transconductance to drain current ratio (g m /I d ). In the high |V gst | linear regime, the σ(∆I d )/I d for the strained device is smaller than that of the unstrained one because of its smaller normalized current factor mismatch. In the high |V gst | saturation regime, the improvement in the σ(∆I d )/I d for the strained device is further enhanced because of the reduced critical electric field at which the carrier velocity becomes saturated.

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

“…Due to both the exponential nature and the increased I D variability in this operating regime at cryogenic temperatures, Taylor expansion of Eq. (2) becomes impractical, thus making it more appropriate to use a logarithmic transform with base 10 [14], [17]:…”

“…There is evidence in literature indicating a deterioration of mismatch at low temperatures [9]- [11], thus stressing even more the importance of the cryogenic modeling of this effect. Mismatch has been studied extensively over the military temperature range (−55-125 • C) [9]- [13], including the subthreshold region [14]- [20]. Work on cryogenic device mismatch, however, has been limited to moderate to strong inversion [21]- [24].…”