Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Hart, P. A. 't; Babaie, Masoud; Charbon, Edoardo; Vladimirescu, Andrei; Foti, Sebastiano

doi:10.1109/jeds.2020.2988730

Cited by 26 publications

(12 citation statements)

References 30 publications

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“…1c, d [22]. Moreover, the degradation of active device matching [23] and the improvement of the quality factor of on-chip passive components [24], necessitate careful characterization and modeling for circuits operated at cryogenic temperatures.…”

mentioning

confidence: 99%

CMOS-based cryogenic control of silicon quantum circuits

Xue,

Patra,

van Dijk

et al. 2020

Preprint

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mentioning

confidence: 99%

CMOS-based cryogenic control of silicon quantum circuits

Xue,

Patra,

van Dijk

et al. 2020

Preprint

Self Cite

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“…Due to the cryogenic shift in device performance and the numerical instability in the foundry device models when extrapolated beyond their range of validity, also standard foundry models cannot be used at cryogenic temperatures. Still, by comparing characterization data [25], [26] at 300 and 4.2 K, boundaries for the main relevant changes in device and circuit behavior can be derived to ensure robust circuit design, although unfortunately no circuit simulations can be performed.…”

Section: Cryo-cmos Design Challengesmentioning

confidence: 99%

Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K

van Staveren,

Padalia,

Charbon

et al. 2024

IEEE J. Solid-State Circuits

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This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in weak inversion to achieve continuous operation from room temperature (RT) down to cryogenic temperatures. Their accuracy limitations due to curvature, body effect, and mismatch are investigated and experimentally validated. Implemented in 40-nm CMOS, the references show a line regulation better than 2.7%/V from a supply as low as 0.99 V. By applying dynamic element matching (DEM) techniques, a spread of 1.2% (3σ ) from 4.2 to 300 K can be achieved, resulting in a temperature coefficient (TC) of 111 ppm/K. As the first significant statistical characterization extending down to cryogenic temperatures, the results demonstrate the ability of the proposed architectures to work under cryogenic harsh environments, such as space-and quantumcomputing applications.

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“…The sub-DACs are then sequentially enabled to create a symmetric pulse of current, which is filtered and upconverted. This approach guarantees a smooth pulse due to the inherent monotonicity of the rising and falling edges, overcoming challenges related to MOSFET mismatch degradation at cryogenic temperatures [48], [49]. The mixer center tap is grounded through a balance resistor, providing a ground return for the single-ended current pulse.…”

Section: A Xy Controllermentioning

confidence: 99%

Design and Characterization of a <4-mW/Qubit 28-nm Cryo-CMOS Integrated Circuit for Full Control of a Superconducting Quantum Processor Unit Cell

Yoo,

Chen,

Arute

et al. 2023

IEEE J. Solid-State Circuits

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A universal fault-tolerant quantum computer will require large-scale control systems that can realize all the waveforms required to implement a gateset that is universal for quantum computing. Optimization of such a system, which must be precise and extensible, is an open research challenge. Here, we present a cryogenic quantum control integrated circuit (IC) that is able to control all the necessary degrees of freedom of a two-qubit subcircuit of a superconducting quantum processor. Specifically, the IC contains a pair of 4-8-GHz RF pulse generators for XY control, three baseband current generators for qubit and coupler frequency control, and a digital controller that includes a sequencer for gate sequence playback. After motivating the architecture, we describe the circuit-level implementation details and present experimental results. Using standard benchmarking techniques, we show that the cryogenic CMOS (cryo-CMOS) IC is able to execute the components of a gateset that is universal for quantum computing while achieving single-qubit XY and Z average gate error rates of 0.17%-0.36% and 0.14%-0.17%, respectively, as well as two-qubit average cross-entropy benchmarking (XEB) cycle error rates of 1.2%. These error rates, which were achieved while dissipating just 4 mW/qubit, are comparable to the measured error rates obtained using baseline room-temperature electronics.

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Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Abstract: This work was supported by Intel.

Cited by 26 publications

References 30 publications

CMOS-based cryogenic control of silicon quantum circuits

CMOS-based cryogenic control of silicon quantum circuits

Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K

Design and Characterization of a <4-mW/Qubit 28-nm Cryo-CMOS Integrated Circuit for Full Control of a Superconducting Quantum Processor Unit Cell

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