Introduction

Abstract

ABOUT THIS CHAPTEROver the past three decades, we have seen the semiconductor manufacturing technology advance from 4 microns to 45 nanometers. This shrinkage of feature size has made a dramatic impact on design and test. Now we find system-on-chip (SOC) and system-in-package (SIP) designs that embed more than 100 million transistors running at operating frequencies in the gigahertz range. Within this decade, there will be designs containing more than a billion transistors. These designs can include all varieties of digital, analog, mixed-signal, memory, optical, microelectromechanical systems (MEMS), field programmable gate array (FPGA), and radiofrequency (RF) circuits. Testing designs of this complexity is a significant challenge, if not a serious problem. Data have shown it is beginning to require more than 20% of the development time to generate production test patterns of sufficient fault coverage to detect manufacturing defects.Additionally, when the SOC design is operated in a system, soft errors induced by alpha-particle radiation can adversely force certain memory cells or storage elements to change their states. These soft errors can cause the system to malfunction. As complementary metal oxide semiconductor (CMOS) scaling continues, the combined manufacturing defects and soft errors start to threaten the practicality of these nanometer SOC designs.In this chapter, we first describe the importance of SOC testing and review the design and test challenges reported in the International Technology Roadmap for Semiconductors (ITRS). Next, we outline the Institute of Electrical and Electronics Engineers (IEEE) standards used for testing SOC designs. These include the 1149.1 and 1149.6 boundary-scan standards, the 1500 core-based test and maintenance standard, and the 1149.4 analog boundary-scan standard. Some SOC design Reliability and System AvailabilityTraditionally, component reliability, also called device reliability, is measured by acceptable defect level (defective PPM), failure rate per 1000 hours, noise characteristics, etc. Because process yield and fault coverage affect defect level, reliability screen methods, such as stress testing (through burn-in) and I DDQ testing (by measuring the device leakage currents), are often used to accelerate the failure rate

CDMA bus-based on-chip interconnect infrastructure

“…Command signals -point to a type of current bus activities. and different in respect to solutions presented in [10,11,25,26] relates to the implementation of CDMA encoder and decoder blocks (DED and AE). Namely, instead of classical non-coded data & address bus transfer (see Fig.…”

“…Several different bus-based wrapper architectures, intended for various types of applications, are already described in [9,10,11,25,26,27].…”

“…In [25] an interface wrapper architecture which provides a generally applicable architecture that can provide support to component and interface evolution, diminishing the potential exponential effects of such changes is described. An overall architecture of a SoC with N cores, each wrapped by an IEEE 1500 wrapper is presented in [26]. Wrapper generation tools using a methodology based on assembling of library components in order to produce a Register Transfer Level, RTL, architecture is described in [27].…”

“…In respect to standard wrapper bus-based implementations described in [9,10,11,25,26,27] the main intent of our design proposal was oriented toward the concept of efficient data and address transmission using a CDMA technique. This allow us to up-grade the wrapper architecture but retaining both its function and protocol conversion logic almost unchanged.…”

An Easily Testable Routing Architecture and Prototype Chip

“…In particular, the interconnect network is very complex, and the number of test configurations for interconnects is generally larger than that for logic blocks [8]. The interconnect architecture should be simple in order to reduce the number of test configurations.…”