Introducing Galois field polynomial addition in quantum-dot cellular automata

Mukherjee, Chiradeep; Panda, Saradindu; Mukhopadhyay, Asish K.; Maji, Bansibadan

doi:10.1007/s13204-019-01045-x

Cited by 5 publications

(2 citation statements)

References 55 publications

(65 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The simulations are performed with bistable and coherence vector simulation engines. The QCA design rules (Mukherjee et al , 2019) with a cell size of 18 nm × 18 nm, a center-to-center distance of 20 nm, 5 nm quantum-dot, layer separation of 11.5 nm, a maximum of 15 cascaded cells and minimum of two cascaded cells per clock zone are adopted at 2°K temperature. The dimensions of parameters are selected to make comparison with the existing designs.…”

Section: Proposed Design Approachmentioning

confidence: 99%

Design of efficient multilayer RAM cell in QCA framework

Singh

Sharma

2020

View full text Add to dashboard Cite

Purpose Quantum-dot cellular automata (QCA) is a promising technology, which seems to be the prospective substitute for complementary metal-oxide semiconductor (CMOS). It is a high speed, high density and low power paradigm producing efficient circuits. These days, most of the smart devices used for computing, make use of random access memory (RAM). To enhance the performance of a RAM cell, researchers are putting effort to minimize its area and access time. Multilayer structures in QCA framework are area efficient, fast and immune to the random interference. Unlike CMOS, QCA multilayer architectures can be designed using active components on different layers. Thus, using multilayer topology in the design of a RAM cell, which is not yet reported in the literature can improve the performance of RAM and hence, the computing device. This paper aims to present the modular design of RAM cell with multilayer structures in the QCA framework. The fundamental modules such as XOR gate, 2:1 multiplexer and D latch are proposed here using multilayer formations with the goal of designing a RAM cell with the provision of read, write, set and reset control. Design/methodology/approach All the modules used to design a RAM cell are designed using multilayer approach in QCA framework. Findings The proposed multilayer RAM cell is optimized and has shown an improvement of 20% in cell count, 30% in area, 25% in area latency product and 48.8% in cost function over the other efficient RAM designs with set/reset ability reported earlier. The proposed RAM cell is further analyzed for the fault tolerance and power dissipation. Research limitations/implications Due to the multilayer structure, the complexity of the circuit enhances which can be eliminated using simple architectures. Originality/value The performance metrics and results obtained establish that the multilayer approach can be implemented in the QCA circuit to produce area efficient and optimized sequential circuits such as a latch, flip flop and memory cells.

show abstract

Section: Proposed Design Approachmentioning

confidence: 99%

Design of efficient multilayer RAM cell in QCA framework

Singh

Sharma

2020

View full text Add to dashboard Cite

show abstract

“…It is a combinational circuit that holds input data and then turns them into any output lines. The defective QCA circuits' behavior needs the fault-tolerant demultiplexer schematization [18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

2021

View full text Add to dashboard Cite

Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

show abstract