Design of efficient multilayer RAM cell in QCA framework

Abstract

Purpose Quantum-dot cellular automata (QCA) is a promising technology, which seems to be the prospective substitute for complementary metal-oxide semiconductor (CMOS). It is a high speed, high density and low power paradigm producing efficient circuits. These days, most of the smart devices used for computing, make use of random access memory (RAM). To enhance the performance of a RAM cell, researchers are putting effort to minimize its area and access time. Multilayer structures in QCA framework are area efficient, fast and immune to the random interference. Unlike CMOS, QCA multilayer architectures can be designed using active components on different layers. Thus, using multilayer topology in the design of a RAM cell, which is not yet reported in the literature can improve the performance of RAM and hence, the computing device. This paper aims to present the modular design of RAM cell with multilayer structures in the QCA framework. The fundamental modules such as XOR gate, 2:1 multiplexer and D latch are proposed here using multilayer formations with the goal of designing a RAM cell with the provision of read, write, set and reset control. Design/methodology/approach All the modules used to design a RAM cell are designed using multilayer approach in QCA framework. Findings The proposed multilayer RAM cell is optimized and has shown an improvement of 20% in cell count, 30% in area, 25% in area latency product and 48.8% in cost function over the other efficient RAM designs with set/reset ability reported earlier. The proposed RAM cell is further analyzed for the fault tolerance and power dissipation. Research limitations/implications Due to the multilayer structure, the complexity of the circuit enhances which can be eliminated using simple architectures. Originality/value The performance metrics and results obtained establish that the multilayer approach can be implemented in the QCA circuit to produce area efficient and optimized sequential circuits such as a latch, flip flop and memory cells.

Design of novel multiplexer circuits in QCA nanocomputing

“…(3) Based on these simulation results, the developed 2 to 1 multiplexer circuit has an improvement with regard to cost, cell count, latency and circuit area compared to other 2 to 1 QCA multiplexer circuits in [13,14,15]. Moreover, our developed circuit has advantages with regard to cost, cell count, and circuit area compared to 2 to 1 QCA multiplexer circuits in [6][7][8].…”

“…Moreover, our developed circuit has advantages with regard to cost, cell count, and circuit area compared to 2 to 1 QCA multiplexer circuits in [6][7][8]. The results demonstrate that the proposed 2 to 1 multiplexer circuit reduced the cost by about 50%-85% compared to the circuits that are proposed in [6][7][8][13][14][15]. Although the 2 to 1 multiplexer circuit in [3] has advantages compared to our developed 2 to 1 multiplexer, the architecture of the developed 2 to 1 multiplexer is such that it is suitable for modular design methodology for constructing efficient 2 n to 1 multiplexer circuits.…”

“…In recent years, many different logic circuits have been developed in the QCA technology for various applications, such as QCA multiplier [9], QCA full adder [5,10], QCA multiplexer [3,[6][7][8][9][11][12][13][14][15], QCA counter [16], QCA shift register [17], and QCA comparator [18,19]. In addition, multiplexer circuits play a significant role in the digital circuit design such as arithmetic logic unit design [6].…”

A fault-tolerant design for a digital comparator based on nano-scale quantum-dotcellular automata

“…They have also been investigated and optimized for CMOS technology (Minoglou et al, 2011;Liou, 2018). As a matter of fact, in binary type, a digital comparator receives two inputs and decides if one number is larger than (Singh and Sharma, 2020), smaller than or equal to the other one (Shiri et al, 2019). Due to this importance, the fault-tolerant architecture for the comparators is very required (Sharma, 2020).…”

“…QCA does not use transistors, but this technology is an array or wire of cells, which store information using electrons (Roohi et al, 2015a;Afrooz and Navimipour, 2021). In addition, the QCA-based circuits are capable of highly parallel processing (Singh and Sharma, 2020;Majeed et al, 2019). Main QCA technology's drawback is the incorrect output in the presence of the faults (Seyedi and Navimipour, 2021b).…”