A fault-tolerant design for a digital comparator based on nano-scale quantum-dotcellular automata

Abstract

Purpose Quantum-dot Cellular Automata (QCA) is a new nano-scale transistor-less computing model. To address the scaling limitations of complementary-metal-oxide-semiconductor technology, QCA seeks to produce general computation with better results in terms of size, switching speed, energy and fault-tolerant at the nano-scale. Currently, binary information is interpreted in this technology, relying on the distribution of the arrangement of electrons in chemical molecules. Using the coplanar topology in the design of a fault-tolerant digital comparator can improve the comparator’s performance. This paper aims to present the coplanar design of a fault-tolerant digital comparator based on the majority and inverter gate in the QCA. Design/methodology/approach As the digital comparator is one of the essential digital circuits, in the present study, a new fault-tolerant architecture is proposed for a digital comparator based on QCA. The proposed coplanar design is realized using coplanar inverters and majority gates. The QCADesigner 2.0.3 simulator is used to simulate the suggested new fault-tolerant coplanar digital comparator. Findings Four elements, including cell misalignment, cell missing, extra cell and cell dislocation, are evaluated and analyzed in QCADesigner 2.0.3. The outcomes of the study demonstrate that the logical function of the built circuit is accurate. In the presence of a single missed defect, this fault-tolerant digital comparator architecture will achieve 100% fault tolerance. Also, this comparator is above 90% fault-tolerant under single-cell displacement faults and is above 95% fault-tolerant under single-cell missing defects. Originality/value A novel structure for the fault-tolerant digital comparator in the QCA technology was proposed used by coplanar majority and inverter. Also, the performance metrics and obtained results establish that the coplanar design can be used in the QCA circuits to produce optimized and fault-tolerant circuits.

Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

“…The deposition phase is where quantum‐dot CA technology has flaws. Figure 3 depicts a variety of abnormalities that can be grouped into three categories: cell omission, cell displacement, and additional cell deposition 15,16 …”

“…Figure 3 depicts a variety of abnormalities that can be grouped into three categories: cell omission, cell displacement, and additional cell deposition. 15,16 F I G U R E 1 Quantum-dot cellular automata (CA) basics; (A) quantum-dot CA cells, (B) inverter gate, and (C) majority gate…”

Analysis and design of a new fault‐tolerant digital comparator based on nano‐scale quantum technology

“…Nanoscience and nanotechnologies have recently gotten a lot of press. [1][2][3] In digital systems, compared to CMOS, 4,5 Quantum-dot cellular automata (QCA) technology implements advanced VLSI designs with exceptionally reduced energy usage and achieves outstanding low speed at the nano-scale. 6 Furthermore, the voltage and current in CMOS technology reflect binary values.…”

“…17,18 Comparators are also widely used in processing units and microcontrollers. 2,19 Hence, a fault-tolerant comparator design is essential. This work presents a fault-tolerant comparator architecture that will tolerate any defect by one cell.…”

“…In contrast, fault‐tolerant design for comparator has received less study attention recently 17,18 . Comparators are also widely used in processing units and microcontrollers 2,19 . Hence, a fault‐tolerant comparator design is essential.…”