Interface states and related surface currents in SiC junctions

Codreanu, C.; Avram, Mărioara; Obreja, V.V.N.; Voitincu, C.; Codreanu, I.

doi:10.1109/smicnd.2003.1252439

Cited by 8 publications

(1 citation statement)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The surface states are assumed to distribute uniformly within 10Å from the surface. Their densities (N S ) was set to 1e14cm -2 while the electron and hole capture cross-sections were assumed to be n = 10 -14 cm -2 and p = 6 10 -15 cm -2 , respectively [6].…”

Section: Physical Modelmentioning

confidence: 99%

Two-Dimensional Analysis of the Surface Trap Effect on Gate Lag Phenomena in 4H-SiC MESFET

Deng

Zhang

et al. 2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

View full text Add to dashboard Cite

The surface-trap effect on the gate lag in 4H-SiC MESFET's is investigated by a two-dimensional device simulation, and the DC and gate lag characteristics dependence on the trap level and the suface trap density have been studied. It is shown that the drain saturation current are reduced by the presence of surface traps. When the the energy level of the surface traps is located in the lower half of the energy gap, the gate lag becomes remarkable. This is because the thickness of surface depletion region can significantly change with the applied gate voltage. As a result, devices with lower surface state density can efficiently degrade the gate lag phenomenon.

show abstract

Section: Physical Modelmentioning

confidence: 99%