Two-Dimensional Analysis of the Surface Trap Effect on Gate Lag Phenomena in 4H-SiC MESFET

Abstract

The surface-trap effect on the gate lag in 4H-SiC MESFET's is investigated by a two-dimensional device simulation, and the DC and gate lag characteristics dependence on the trap level and the suface trap density have been studied. It is shown that the drain saturation current are reduced by the presence of surface traps. When the the energy level of the surface traps is located in the lower half of the energy gap, the gate lag becomes remarkable. This is because the thickness of surface depletion region can significantly change with the applied gate voltage. As a result, devices with lower surface state density can efficiently degrade the gate lag phenomenon.