Interconnection Wire-Length Estimation in Vlsi Standard Cell Placement via Neural Network

Saxena, Ashutosh; George, S.; Rambabu, P.

doi:10.1142/s0218213098000202

Cited by 2 publications

(3 citation statements)

References 10 publications

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“…In [11] a neural network is used to estimate the wirelength during VLSI standard cell placement. In this paper, the neural networks are trained to predict the wirelength of the digital circuits mapped on the homogeneous FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Neural network based pre-placement wirelength estimation

Liu

Zhang

2012

2012 International Conference on Field-Programmable Technology

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We propose a neural network based approach for estimating the total wirelength of a digital circuit, mapped onto an FPGA, before circuit placement and routing. A 3-layer MLP neural network is trained to learn the behavior of a placement tool and then quickly predicts the wirelength of a circuit design with the accuracy similar to one obtained after placement. A priori knowledge about the wirelength of circuit designs can be used to effectively guide the design exploration processes at the early design stages. This breaks the repetitive CAD design flow and reduces the design cycle. In this work, five circuit parameters and two FPGA architecture parameters are considered in the wirelength estimation. The proposed approach is evaluated by comparing the wirelength given by the trained neural networks and the placement tool VPR for the IWLS2005 circuit benchmark. Results show that the neural network's estimation has an average error below 0.6% compared to VPR. The neural network model is also compared to a linear model for the wirelength estimation, showing 7.39 times improvement in the estimation accuracy.

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Section: Introductionmentioning

confidence: 99%

Neural network based pre-placement wirelength estimation

Liu

Zhang

2012

2012 International Conference on Field-Programmable Technology

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“…This approach does not introduce any assumptions about the relationship between the parameters, and learns the actual relation instead. In [16] and [17], a classical multilayer perceptron (MLP) NN was used to estimate the wirelength of VLSI and FPGA implementations of circuits, respectively. Unlike [16] and [17], the present approach uses a KBNN to model the channel width.…”

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confidence: 99%

“…In [16] and [17], a classical multilayer perceptron (MLP) NN was used to estimate the wirelength of VLSI and FPGA implementations of circuits, respectively. Unlike [16] and [17], the present approach uses a KBNN to model the channel width. The model is built on top of the existing analytical formulas of the channel width and thus contains the intuitive architecture information that the classical NN does not provide.…”

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confidence: 99%

Knowledge-Based Neural Network Model for FPGA Logical Architecture Development

Liu

Gao

Zhang

2016

IEEE Trans. VLSI Syst.

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This paper proposes a knowledge-based neural network (KBNN) modeling approach for field-programmable gate array (FPGA) logical architecture design. The KBNN embeds the existing FPGA analytical models (AMs) into an NN. The NN can complement the AMs according to their needs to provide further increased model accuracy, while maintaining the meaningful trends successfully captured in the AMs. The obtained KBNN predicts the routing channel width required by circuit implementations on various FPGA architectures, which can be used by architects to quickly and accurately evaluate various FPGA architectures in early development stages. Experimental results show that the KBNN-based approach achieves an average error of 2%, which shows 75% accuracy enhancement over the existing AMs for routing channel width estimation of a set of benchmark circuits and FPGA architectures. The KBNN model has been applied to three FPGA architecture development scenarios to demonstrate its practical application and effectiveness.Index Terms-Field-programmable gate array (FPGA) architecture design, knowledge-based neural network (KBNN), modeling.

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Interconnection Wire-Length Estimation in Vlsi Standard Cell Placement via Neural Network

Cited by 2 publications

References 10 publications

Neural network based pre-placement wirelength estimation

Neural network based pre-placement wirelength estimation

Knowledge-Based Neural Network Model for FPGA Logical Architecture Development

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