Neural network based pre-placement wirelength estimation

Abstract

We propose a neural network based approach for estimating the total wirelength of a digital circuit, mapped onto an FPGA, before circuit placement and routing. A 3-layer MLP neural network is trained to learn the behavior of a placement tool and then quickly predicts the wirelength of a circuit design with the accuracy similar to one obtained after placement. A priori knowledge about the wirelength of circuit designs can be used to effectively guide the design exploration processes at the early design stages. This breaks the repetitive CAD design flow and reduces the design cycle. In this work, five circuit parameters and two FPGA architecture parameters are considered in the wirelength estimation. The proposed approach is evaluated by comparing the wirelength given by the trained neural networks and the placement tool VPR for the IWLS2005 circuit benchmark. Results show that the neural network's estimation has an average error below 0.6% compared to VPR. The neural network model is also compared to a linear model for the wirelength estimation, showing 7.39 times improvement in the estimation accuracy.

Knowledge-Based Neural Network Model for FPGA Logical Architecture Development

“…Five basic parameters of a digital circuit, namely, the number of two-input logic gates (n 2 ), the number of nets, the logic depth, the number of IOs, and the maximum fanout have been considered in [17]. We extract these parameters from the benchmark circuits used earlier and calculate the correlation factors between these circuit parameters and the channel width obtained based on an FPGA architecture.…”

“…This approach does not introduce any assumptions about the relationship between the parameters, and learns the actual relation instead. In [16] and [17], a classical multilayer perceptron (MLP) NN was used to estimate the wirelength of VLSI and FPGA implementations of circuits, respectively. Unlike [16] and [17], the present approach uses a KBNN to model the channel width.…”

“…In [16] and [17], a classical multilayer perceptron (MLP) NN was used to estimate the wirelength of VLSI and FPGA implementations of circuits, respectively. Unlike [16] and [17], the present approach uses a KBNN to model the channel width. The model is built on top of the existing analytical formulas of the channel width and thus contains the intuitive architecture information that the classical NN does not provide.…”

Estimating circuit delays in FPGAs after technology mapping

“…However, similar literature can be found: extensive research considered local wirelength estimations [5] and total wirelength estimations [4]. In [3] fast placement was used as an early timing feedback model for improved technology mapping.…”

“…Both depend on the wirelength behavior. Studies have been dedicated to the estimation of local [5] and global [4] wirelengths, but to our knowledge both performance estimations and identification of the critical zone are not present in literature. Therefore this paper, firstly, presents a comparison of three performance estimation techniques: logic depth, Monte Carlo simulation and fast placement (ordered from low to high accuracy and runtime).…”