Knowledge-Based Neural Network Model for FPGA Logical Architecture Development

Liu, Qiang; Gao, Ming; Zhang, Qi‐Jun

doi:10.1109/tvlsi.2015.2412958

Cited by 7 publications

(4 citation statements)

References 22 publications

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“…The algorithm was configured to optimize arithmetic operations in parallel using the same clock cycle. Thus, in (12), for example, the first operation of multiplication was performed in parallel with the subtraction, that is, both operations were processed during the same five clock cycles. Then, three other operations were performed sequentially, multiplication, subtraction and division, so the result was computed with 30 clock cycles.…”

Section: Resultsmentioning

confidence: 99%

“…Thus, (10) is transformed in ( 11)- (13). These three equations act to regulate the error of different instants of time, been (11) responsible for the current instant, (12) previous instant and ( 13) for the instant before the PD.…”

Section: Pid Controllermentioning

confidence: 99%

“…The use of FPGA in RTDS is noticeable in many engineering domains, such as electrical power [2,3], drive systems [10,11], and artificial intelligence [12]. FPGAs have seen a massive evolution since their inception almost three decades ago [13].…”

Section: Introductionmentioning

confidence: 99%

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Embedding an Electrical System Real-Time Simulator with Floating-Point Arithmetic in a Field Programmable Gate Array

et al. 2021

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Real-Time Digital Simulation (RTDS) is a powerful tool in modeling and analyzing electrical and drive systems because it provides an efficient and accurate process. There are several hardware devices for this type of simulation; however, their high costs have led to the increasing use of more affordable and reconfigurable technologies. In this context, many logic blocks and storage elements make the Field Programmable Gate Array (FPGA) an ideal device to perform RTDS. This work proposes a technique to embed a real-time digital simulator in an FPGA through Hardware Description Language (HDL) since it provides liberty in the architecture choice and no dependency on commercial ready-made hardware–software packages. The approach proposed focuses on system design developing with expression tree graph, synthesizing and verifying, prioritizing the performance and design accuracy concerning area and power consumption. Thus, the result acquisition occurs at a time step considered in real-time. A simulation of a direct current (DC) motor speed control has been incorporated into this work as an example of application, which includes the embedding and simulation of the electric machine and its drive system. Performance tests have shown that the developed simulator is real-time and makes possible realistic analysis of the interaction between the plant and its control. In addition, an idea of the hardware requirement for real-time simulation is proposed based on the number of mathematical operations.

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Section: Resultsmentioning

confidence: 99%

Section: Pid Controllermentioning

confidence: 99%

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Embedding an Electrical System Real-Time Simulator with Floating-Point Arithmetic in a Field Programmable Gate Array

et al. 2021

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“…It is important to mention here that the aforementioned state-of-the-art work mostly uses ML or artificial intelligence to optimize the auto tuning of the parameters for FPGA backend flow. These frameworks obtain the desired results through extensive training of underlying ML algorithms, such as Support Vector Machine (SVM) [26], Bayesian Learning (BL) and Knowledge-Based Neural Networks (KBNN) [27].…”

Section: Related Workmentioning

confidence: 99%

Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning

Baig

Farooq

2022

Electronics

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Over the past few years, the computation capability of field-programmable gate arrays (FPGAs) has increased tremendously. This has led to the increase in the complexity of the designs implemented on FPGAs and to the time taken by the FPGA back-end flow. The FPGA back-end flow comprises of many steps, and routing is one of the most critical steps among them. Routing normally constitutes more than 50% of the total time taken by the back-end flow and an optimization at this step can lead to overall optimization of the back-end flow. In this work, we propose enhancements to the routing step by incorporating a reinforcement learning (RL)-based framework. In the proposed RL-based framework, we use the ϵ-greedy approach and customized reward functions to speed up the routing step while maintaining similar or better quality of results (QoR) as compared to the conventional negotiation-based congestion-driven routing solution. For experimentation, we use two sets of widely deployed, large heterogeneous benchmarks. Our results show that, for the RL-based framework, the ϵ-greedy greedy approach combined with a modified reward function gives better results as compared to purely greedy or exploratory approaches. Moreover, the incorporation of the proposed reward function in the RL-based framework and its comparison with a conventional routing algorithm shows that the proposed enhancement requires less routing time while giving similar or better QoR. On average, a speedup of 35% is recorded for the proposed routing enhancement as compared to negotiation-based congestion-driven routing solutions. Finally, the speedup of the routing step leads to an overall reduction in the execution time of the back-end flow of 25%.

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