Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies

Zürcher, P.; Alluri, P.; Chu, Peir; Duvallet, A.; Happ, C.; Henderson, Rashaunda; Mendonca, J.; Kim, M.; Petras, M.; Raymond, M.; Remmel, T.; Roberts, D.H.; Steimle, B.; Stipanuk, J.; Straub, S.; Sparks, T.; Tarabbia, M.; Thibieroz, H.; Miller, M.

doi:10.1109/iedm.2000.904281

Cited by 44 publications

(18 citation statements)

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“…Unlike CMOS capacitors that are built in the device layer, MIM capacitors are fabricated between metal layers. These structures have high capacitance density and low leakage current density [3,18,34,35,40,50]. However, MIM decaps cannot be used unconditionally to replace CMOS decaps, since their use incurs a cost: they present routing blockages to nets that attempt to cross them.…”

Section: Decap Allocationmentioning

confidence: 98%

Thermal and Power Delivery Challenges in 3D ICs

Jain

Zhou

Kim

et al. 2009

Integrated Circuits and Systems

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Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines solution schemes to overcome the corresponding bottlenecks.

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Section: Decap Allocationmentioning

confidence: 98%

Thermal and Power Delivery Challenges in 3D ICs

Jain

Zhou

Kim

et al. 2009

Integrated Circuits and Systems

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“…Interconnect metals can be used to form resistors, but because of their low sheet resistance they are typically only used in a small number of special applications. Precision analog resistors are provided in some specialty technologies [17], but because of the added cost and complexity the use of standard diffused and poly resistors is preferred. Poly resistors in modern technologies can be designed to have small voltage and temperature coefficients, and they have much lower parasitic capacitance than diffused resistors, and so are preferred for many applications.…”

Section: Polysilicon Resistorsmentioning

confidence: 99%

RF CMOS is more than CMOS: Modeling of RF passive components

McAndrew¹

2009

2009 IEEE Custom Integrated Circuits Conference

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This paper details recent progress in modeling some RF CMOS passive components: inductors, transformers, and resistors. Many different topologies have been proposed for networks to model spiral inductors; these are analyzed and shown to trend toward reviving the one-segment (π-or T-topology) approach. The need to account for the distributed nature of metal windings and coupling through a lossy substrate is emphasized. On-chip transformer models are discussed, and shown to need further development. Details of accurate physical modeling of polysilicon resistors, including nonlinearities and frequency dependence from both parasitics and self-heating, are provided.

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“…The use of MIM capacitors in these applications has attracted great attention because of their highly conducting electrodes and low parasitic capacitances [21,22,23]. A high capacitance density is required for a MIM capacitor to allow for small area, to increase the circuit density, and to further reduce the manufacturing costs.…”

Section: Fields Of Applicationsmentioning

confidence: 99%

High-K: Latest Developments and Perspectives

Bauer

Lemberger

Erlbacher

et al. 2008

MSF

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Abstract. The paper reviews recent progress and current challenges in implementing high-k dielectrics in microelectronics. Logic devices, non-volatile-memories, DRAMs and low power mixedsignal components are found to be the technologies where high-k dielectrics are implemented or will be introduced soon. Two gate architectures have to be considerd: MOS with metal as gate electrode and MIM. In particular, Hf-silicates for logic and NVM devices in conventional MOS architecture and ZrO 2 for DRAM cells in MIM architecture are discussed. Fields of applicationsThe breakthrough and thus the enormous growth of the microelectronics, especially in the Information Technology, in the past few decades is based, to a large extend, on the SiO 2 /Si system which was therefore called "a simple gift of nature". Gate dielectrics consisting of ultra thin silicon dioxide layers are the key element in conventional silicon based microelectronic devices. In the very beginning of the microelectronics, the thickness of the SiO 2 gate oxide was a few hundred nanometers. Nowadays, state-of-the-art MOSFETs (metal oxide semiconductor field effect transistor) require gate oxide thicknesses of just a few atomic layers. Until recently, the continuous scaling of the ULSI (ultra large scale integration) devices has been accomplished by shrinking physical dimensions. Physical gate oxides with physical thicknesses in the range of 1.6 nm are currently fabricated and thicknesses below 1.0 nm will be requested for future device generations [1]. In this thickness range, key dielectric parameters degrade, like gate leakage current, channel mobility, reliability etc. [2,3,4]. Thus, the necessity arises to replace the SiO 2 with a dielectric of higher permittivity [5,6]. Application of oxides with a higher dielectric constant (high-k) allows for a physically thicker insulating layer with the same capacitance per unit area as that required for SiO 2 . The so-called equivalent oxide thickness (EOT) is defined as follows: EOT = d high-k · k SiO2 / k high-k .(1) d high-k is the physical oxide thickness, k SiO2 and k high-k are the dielectric constant of the silicon dioxide and the high-k oxide, respectively. But, the high-k dielectric has to satisfy several requirements to fulfil all the demands of state-of-the-art gate dielectrics. First, it has to be thermodynamically stable in contact with silicon [7], it must be process compatible with CMOS (complementary MOS) and withstand source/drain implant annealing, oxygen diffusion should be low to prevent generation of a sizeable SiO 2 interface layer (IL) or trapping defects [8], and it must have sufficiently high band offsets to act as barrier for electrons and holes [9]. Also, the high-k oxide has to show a high quality interface to silicon, with only few interface or defect states within the silicon band gap, be- Online: 2008-03-24 ISSN: 1662-9752, Vols. 573-574, pp 165-180 doi:10.4028/www.scientific.net/MSF.573-574.165 © 2008 This is an open access article under the CC-BY 4.0 license (https://creativecomm...

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Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies

Cited by 44 publications

References 0 publications

Thermal and Power Delivery Challenges in 3D ICs

Thermal and Power Delivery Challenges in 3D ICs

RF CMOS is more than CMOS: Modeling of RF passive components

High-K: Latest Developments and Perspectives

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