This paper addresses misconceptions about MOS-FET mismatch for analog desi . V, mismatch does not follow a simplistic 1/( s " area) law, especially for widelshort and narrowllong devices, which are common geometries in analog circuits. Further, V, and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in prediction of mismatch. This model is applied to MOS-FET current mirrors to show some non-obvious effects over bias, geometry, and multiple unit devices.

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