Integration of power devices in advanced mixed signal analog BiCMOS technology

Efland, T.

doi:10.1016/s0026-2692(01)00011-8

Cited by 21 publications

(3 citation statements)

References 21 publications

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“…On the other hand, the use of a shallow N-drift diffusion (SN-drift) instead of the DNdrift also provides PT breakdown protection. Nevertheless, this solution should be accompanied by a previous formation of an N-type buried layer beneath the SN-drift to prevent a premature drift depletion process [10,11]. Another proposed solution for avoiding PT is the use of a P-type buried layer under a DN-drift diffusion to enhance the depletion process for proper RESURF action [12].…”

Section: Design Solutions For Avoiding Punch-throughmentioning

confidence: 99%

Analysis of punch-through breakdown in bulk silicon RF power LDMOS transistors

Cortés

Fernández-Martínez

Flores

et al. 2008

Microelectronics Reliability

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Section: Design Solutions For Avoiding Punch-throughmentioning

confidence: 99%

Analysis of punch-through breakdown in bulk silicon RF power LDMOS transistors

Cortés

Fernández-Martínez

Flores

et al. 2008

Microelectronics Reliability

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“…Although the total width of the TSJLDMOS structure half-cell is increased, R on can be further reduced since there is a lower negative effect of the doping transition between pillars and a lower currentcrowding effect due to wider conduction path created by the trench lateral gate. Nevertheless, the TSJLDMOS structure requires additional work with respect to V TH control since the vertical and channel P-body profiles are different [19].…”

Section: Trench Lateral Gate In Sjldmos Transistorsmentioning

confidence: 99%

Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates

Cortés¹,

Fernández-Martínez²,

Flores³

et al. 2007

Semicond. Sci. Technol.

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This paper is addresses the analysis of the super-junction (SJ) concept applied to LDMOS transistors in thin-SOI technology. Extensive numerical simulations have been carried out to investigate their suitability for low-voltage power applications. The static and dynamic performances of different SJLDMOS structures have been studied in comparison with a conventional RESURF LDMOS structure with the same SOI substrate. In order to improve the current-crowding effect at the body/drift region, the inclusion of a trench lateral gate in the SJ structure (TSJLDMOS) is proposed to further decrease the total on-state resistance (R on ) value maintaining the same voltage capability. The increment of the N + source and N-drift diffusion area overlapping the gate terminal leads to a gate-related capacitance enhancement. Although very low R on results can be obtained, the capacitance degradation limits the suitability of TSJLDMOS structure in RF power amplifiers.

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“…Advancements were made enabling LDMOS power transistor to exhibit low ON-state resistance and high breakdown capability concurrently through a reduced surface field (RESURF) technology [4][5][6][7][8]. However, this RESURF technology can not be used in a BiCMOS process providing CMOS, vertical NPN transistor and power LDMOS transistor at the same time [9][10][11][12][13]. This is because vertical NPN transistor and RESURF LDMOS transistor require different epitaxial thicknesses according to their breakdown voltages.…”

Section: Introductionmentioning

confidence: 99%

Design of complementary LDMOS in 0.35 μm BiCMOS technology for smart integration

Abouelatta

Gontrand

Zekry

2011

Eur. Phys. J. Appl. Phys.

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In this paper, an nLDMOS and a pLDMOS are developed by slight modifications of the base process steps of 0.35µm BiCMOS technology. Extra two masks are used for the formation of the body region and the drift region with slightly added thermal budget and without resorting to high-tilt implants. The specific ON-resistance (R ON,SP) and the OFF-state breakdown voltage(BV) are 1.5 mΩ.cm 2 and 60V, for the nLDMOS and 3.0 mΩ.cm 2 and 160V, for the pLDMOS, so the devices can typically be operated around 42V supply voltage, which is suitable for the new automotive applications. An isolation mechanism, between the power devices is suggested using a deep trench filled with silicon dioxide and undoped polysilicon. The polysilicon has a nearly perfect conformal deposition, that is, both step coverage and bottom coverage are 100%. A simple subcircuit model is built using a two module approach, one for the intrinsic MOS area and the other for the drift region. The Spice model parameters of the intrinsic MOS part are extracted using a system that links the ICCAP extraction tool with the results of the ISE-TCAD tools. The simulation results using the Spice model are compared to the results provided by ISE-TCAD tools, and the accuracy at room temperature is less than 5% for the whole voltage domain. An interface circuit, to convert 0/3.3 V to 0/42 V, suitable for automotive applications, is proposed.

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Integration of power devices in advanced mixed signal analog BiCMOS technology

Cited by 21 publications

References 21 publications

Analysis of punch-through breakdown in bulk silicon RF power LDMOS transistors

Analysis of punch-through breakdown in bulk silicon RF power LDMOS transistors

Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates

Design of complementary LDMOS in 0.35 μm BiCMOS technology for smart integration

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