Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates

Abstract

This paper is addresses the analysis of the super-junction (SJ) concept applied to LDMOS transistors in thin-SOI technology. Extensive numerical simulations have been carried out to investigate their suitability for low-voltage power applications. The static and dynamic performances of different SJLDMOS structures have been studied in comparison with a conventional RESURF LDMOS structure with the same SOI substrate. In order to improve the current-crowding effect at the body/drift region, the inclusion of a trench lateral gate in the SJ structure (TSJLDMOS) is proposed to further decrease the total on-state resistance (R on ) value maintaining the same voltage capability. The increment of the N + source and N-drift diffusion area overlapping the gate terminal leads to a gate-related capacitance enhancement. Although very low R on results can be obtained, the capacitance degradation limits the suitability of TSJLDMOS structure in RF power amplifiers.

Analysis and optimization of safe-operating-area of LUDMOS transistors based on 0.18 µm SOI CMOS technology

“…In the case of SJ-LUDMOS, the N-well is also referred to as the N-pillar concentration which could be higher thanks to P/N pillar lateral depletion. Besides, the N-pillar concentration higher than that of the P-pillar (4 × 10 16 cm −3 ) is required to compensate for the substrateassisted depletion [8]. A better approach to almost eliminate this degradation effect is the use of N-type surface implantation steps in the N-pillar [10], or the inclusion of an N-type buffer layer [11]; this last case being for bulk technology.…”

“…On the other hand, the superjunction (SJ) concept [6], which applies the 3D RESURF technique in the LDD region, allows a further reduction of R on-sp at a given voltage, thus further improving the R on-sp /V BR trade-off obtained in conventional RESURF LDMOS structures. However, the efficiency of this technique diminishes when LDMOS device dimensions are shrunk since the requirement of deep and narrow high doped P/N pillars are prone to degradation effects such as charge imbalance, P/N pillars doping inter-diffusion and current crowding at the 0268-1242/10/045013+07$30.00 gate-drift region [7,8]. However, although it is well documented that both STI and SJ technologies applied in the LDD region lead to better R on-sp /V BR performance, only a few papers analyzed its electrical SOA [6], especially those concerning superjunction concept applied in LDMOS transistors.…”

Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors

“…The performance of the SJ LDMOS structure for low-voltage applications requires narrow and high-doped P/N pillars in the LDD, which are prone to degradation effects such as charge imbalance, P/N pillars doping inter-diffusion and current crowding at the gate/drift region. These degradations combined with their technological design difficulties do not allow us to improve the conventional single-RESURF R ON-sp /V BR trade-off results when the width of the device and pillars is scaled down [4]. A second approach is the cell-pitch reduction which is done by placing an oxide trench in the LDMOS drift region to have quasi-vertical conduction and to improve the R ON-sp /V BR trade-off [5][6][7].…”