Design of complementary LDMOS in 0.35 μm BiCMOS technology for smart integration

Abstract

In this paper, an nLDMOS and a pLDMOS are developed by slight modifications of the base process steps of 0.35µm BiCMOS technology. Extra two masks are used for the formation of the body region and the drift region with slightly added thermal budget and without resorting to high-tilt implants. The specific ON-resistance (R ON,SP) and the OFF-state breakdown voltage(BV) are 1.5 mΩ.cm 2 and 60V, for the nLDMOS and 3.0 mΩ.cm 2 and 160V, for the pLDMOS, so the devices can typically be operated around 42V supply voltage, which is suitable for the new automotive applications. An isolation mechanism, between the power devices is suggested using a deep trench filled with silicon dioxide and undoped polysilicon. The polysilicon has a nearly perfect conformal deposition, that is, both step coverage and bottom coverage are 100%. A simple subcircuit model is built using a two module approach, one for the intrinsic MOS area and the other for the drift region. The Spice model parameters of the intrinsic MOS part are extracted using a system that links the ICCAP extraction tool with the results of the ISE-TCAD tools. The simulation results using the Spice model are compared to the results provided by ISE-TCAD tools, and the accuracy at room temperature is less than 5% for the whole voltage domain. An interface circuit, to convert 0/3.3 V to 0/42 V, suitable for automotive applications, is proposed.

Design considerations of high voltage RESURF nLDMOS: An analytical and numerical study

“…The technique provides the ability to form high-voltage lateral devices using an inherently low-voltage IC technology [8][9][10].…”

“…is the concentration which achieves maximum breakdown voltage of the structure and gives the best trade-off between the breakdown voltage and the ON-resistance. This occurs by applying the optimum RESURF'ing condition [9,10]. Figure 1 The schematic cross-section of the RESURF LDMOS.…”