Design considerations of high voltage RESURF nLDMOS: An analytical and numerical study

Abstract

In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35 lm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent R ON,SP /BV trade-off (BV % 400 V and R ON,SP = 9.5 mX cm 2 for T epi = 4 lm and L Drift = 17 lm) without any added process complexity. The maximum obtained drain current is 1.8 mA/lm at a gate voltage of 5 V. The designed device is suitable for smart power integration. Ó 2014 Faculty of Engineering, Ain Shams University. Production and hosting by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

Experimental Analysis of 600V 4H-SiC Vertical and Lateral MOSFETs Fabricated on the same 6-Inch Substrate Using a Single Process

“…The overall result for the VMOS shows better electrical characteristics, while LMOS shows more room for improvement. The performance of the LMOS can be further engineered by optimizing the drift layer, device, and layout design rules [8,9].…”