Instruction based power consumption estimation methodology

Caldari, M.; Conti, Massimo; Crippa, Paolo; Nuzzo, G.; Orcioni, Simone; Turchetti, Claudio

doi:10.1109/icecs.2002.1046270

Cited by 14 publications

(5 citation statements)

References 5 publications

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“…Further models have been proposed at higher levels. In [2] an analytical model is derived to estimate the power consumption based on the information from gate-level simulations such as number of gates, switching activity and model coefficients. A behavior-level model is further derived to estimate the average switching activity by monitoring the switching activity of input and output nodes.…”

Section: Area and Power Analysis Toolsmentioning

confidence: 99%

User-friendly approach to capacity planning studies with Java modelling tools

Bertoli¹,

Casale²,

Serazzi³

2009

Proceedings of the Second International ICST Conference on Simulation Tools and Techniques

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Systems-on-Chip (SoC) integrate a complete electronic system in a single integrated circuit. SoCs typically comprise processors, hardware accelerators, memories, and on-chip interconnects. These increasingly complex systems must fulfill many requirements, such as high data throughput, low latency, small area, as well as low power consumption and dissipation.In this paper we show how to evaluate an SoC at Electronic System Level (ESL). We use our performance evaluation framework SystemQ 2.0 not only to analyze common performance metrics, e. g. throughput, latency, and resource utilization, but also to perform area and power estimations at system level. The foundation of our estimations is a large amount of data from synthesized and physically implemented hardware components. From that we build a set of formulas to be integrated into SystemQ.In a case study we show the area and power consumption estimations of a complex SoC interconnect. We reveal how the area and power data are gathered and integrated into SystemQ. Based on real test cases we compare the transistor-level data with the system-level results from SystemQ. It will be shown that the error for the area estimations is up to 6.3 % for single components. The complete system is tested with two standard-cell libraries, whereas the error is 17.0 % and 28.1 %, respectively. The power estimation error is 11.5 % at component level.

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Section: Area and Power Analysis Toolsmentioning

confidence: 99%

User-friendly approach to capacity planning studies with Java modelling tools

Bertoli¹,

Casale²,

Serazzi³

2009

Proceedings of the Second International ICST Conference on Simulation Tools and Techniques

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“…Among the possible abstraction levels, the most important ones are the ESL (Electronic System Level), RTL (Register Trans-fer Level), Gate level and Transistor level [10]. Designers must consider power consumption issues as early as possible to re-duce development time [5].…”

Section: Introductionmentioning

confidence: 99%

“…During the last years researches proposed power consump-tion estimation approaches at ESL [2] [10] [4] [5] [13] [9]. De-pending on the project complexity, it is necessary to combine different elements to provide an adequate power estimation, such as, different estimation approaches, different tools or, dif-ferent programming languages and different abstraction levels.…”

Section: Introductionmentioning

confidence: 99%

An Approach for Power Estimation at Electronic System Level using Distributed Simulation

Oliveira¹,

Brito²,

Araújo³

et al. 2020

JICS

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The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.

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“…Analogue hardware models such as SPICE models provide some of the highest representational quality, but they are not usable for studying entire computers with software running on hardware. For such studies, discrete event models, such as Instruction Set Architecture-(ISA-)accurate [7], cycleaccurate and RTL models [5], are useful when studying functional properties. Instruction Set Simulators (ISS), however, commonly have simulation speeds of the order of a few Million Instructions Simulated per Second (MISPS) [1], [17], and this puts a limit on their usability when the system scales to many-cores, especially for statistical analysis [8].…”

Section: Introductionmentioning

confidence: 99%

Error-Based Metric for Cross-Layer Cut Determination

Rafiev

Xia

Iliasov

et al. 2017

Lecture Notes in Electrical Engineering

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With the increase of system complexity in both platforms and applications, power modelling of heterogeneous systems is facing grand challenges from the model scalability issue. To address these challenges, this paper studies two systematic methods: selective abstraction and stochastic techniques. The concept of selective abstraction via black-boxing is realised using hierarchical modelling and cross-layer cuts, respecting the concepts of boxability and error contamination. The stochastic aspect is formally underpinned by Stochastic Activity Networks (SANs). The proposed method is validated with experimental results from Odroid XU3 heterogeneous 8-core platform and is demonstrated to maintain high accuracy while improving scalability.

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Instruction based power consumption estimation methodology

Cited by 14 publications

References 5 publications

User-friendly approach to capacity planning studies with Java modelling tools

User-friendly approach to capacity planning studies with Java modelling tools

An Approach for Power Estimation at Electronic System Level using Distributed Simulation

Error-Based Metric for Cross-Layer Cut Determination

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