We present the Java Modelling Tools (JMT) suite, an integrated framework of Java tools for performance evaluation of computer systems using queueing models. The suite offers a rich user interface that simplifies the definition of performance models by means of wizard dialogs and of a graphical design workspace. The performance evaluation features of JMT span a wide range of state-of-the-art methodologies including discrete-event simulation, mean value analysis of product-form networks, analytical identification of bottleneck resources in multiclass environments, and workload characterization with fuzzy clustering. The discrete-event simulator supports several advanced modeling features such as finite capacity regions, load-dependent service times, bursty processes, fork-and-join nodes, and implements spectral estimation for analysis of simulative results. The suite is open-source, released under the GNU general public license (GPL), and it is available for free download at: http://jmt.sourceforge.net.

This paper describes JSIM: the simulation module of the Java Modelling Tools (JMT), an open-source fully-portable Java suite for capacity planning studies. The simulator has been purposely developed to help both unexperienced and advanced users. Most of the difficult decisions that are needed in order to run simulations properly, such as the detection of the transient part of samples to be discarded, have been automated. The tool also provides guidance over the graphical design of the network and over the analysis and the plot of the results. What-if parametric analyses for parametric evaluation of complex systems are supported. Several features that increase the generality of the applications to capacity planning studies are provided, among them fork-join service centers, regions with finite capacity, statedependent routing algorithms, priority classes and import of real workload distributions from log files.

Systems-on-Chip (SoC) integrate a complete electronic system in a single integrated circuit. SoCs typically comprise processors, hardware accelerators, memories, and on-chip interconnects. These increasingly complex systems must fulfill many requirements, such as high data throughput, low latency, small area, as well as low power consumption and dissipation.In this paper we show how to evaluate an SoC at Electronic System Level (ESL). We use our performance evaluation framework SystemQ 2.0 not only to analyze common performance metrics, e. g. throughput, latency, and resource utilization, but also to perform area and power estimations at system level. The foundation of our estimations is a large amount of data from synthesized and physically implemented hardware components. From that we build a set of formulas to be integrated into SystemQ.In a case study we show the area and power consumption estimations of a complex SoC interconnect. We reveal how the area and power data are gathered and integrated into SystemQ. Based on real test cases we compare the transistor-level data with the system-level results from SystemQ. It will be shown that the error for the area estimations is up to 6.3 % for single components. The complete system is tested with two standard-cell libraries, whereas the error is 17.0 % and 28.1 %, respectively. The power estimation error is 11.5 % at component level.

In the original article co-Author Tomaso Maria Tobia Villa was missing the institutional affiliation "IRCCS Istituto Ortopedico Galeazzi, Milano, Italy".The original article has been corrected.Publisher's Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

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