Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Raha, Arnab; Jayakumar, Hrishikesh; Raghunathan, Vijay

doi:10.1109/tvlsi.2015.2424212

Cited by 66 publications

(26 citation statements)

References 17 publications

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“…The choice of 8-bits for the inaccurate sub-adders is based on the premise that, for practical digital image processing and video encoding applications, the approximation size is recommended to be confined to the range of 7 to 9 bits in [18,28]. Nevertheless, the number of bits to be allotted to the inaccurate sub-adders can be decided commensurate with a target application depending upon its error resilience.…”

Section: Fpga-based Implementation Resultsmentioning

confidence: 99%

Hardware Optimized and Error Reduced Approximate Adder

Balasubramanian

Maskell

2019

Electronics

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This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)-and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.2 of 15 predominant on approximate logic circuits [12] and approximate arithmetic circuits such as adders and multipliers [13]. Here, the focus is on the design of an approximate adder.Many approximate adders in the existing literature are suited for an application specific integrated circuit (ASIC)-style implementation and only some are suitable for both ASIC-and field programmable gate array (FPGA)-based implementations. Hence, it is unlikely that many approximate adders in the literature, when implemented on an FPGA, would surpass a native accurate FPGA adder of similar size because an FPGA embeds accurate arithmetic units, such as adders and multipliers, which are highly optimized for speed and area.This paper proposes a new approximate adder that is suitable for FPGA-and ASIC-based implementations, and our focus is on a comparison with other approximate adders, which are also suited for FPGA-and ASIC-based implementations. The remainder of this paper is organized as follows. A survey of some popular existing literature on approximate adders is presented in Section 2. Following this, we present the proposed approximate adder (HOERAA) in Section 3. FPGA-based implementation results corresponding to accurate and approximate adders for 32-bit and 64-bit additi...

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Section: Fpga-based Implementation Resultsmentioning

confidence: 99%

Hardware Optimized and Error Reduced Approximate Adder

Balasubramanian

Maskell

2019

Electronics

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“…Acknowledging the necessity to dynamically set the approximation level, considerable research interest is shown on reconfigurable approximate circuits. Reconfigurable approximate adders are produced in [42] by generating a dual state full adder that uses two multiplexers to select between the accurate and approximate results. An approximate carry look-ahead adder is designed in [43] that is able to switch between exact and approximate modes by applying power gating to switch off the exact part.…”

Section: Related Workmentioning

confidence: 99%

“…However, all the aforementioned works apply fixed approximation at design time that cannot be modified at runtime. The ever-growing need for controlling the accuracy of the approximations at runtime is highlighted in [42]- [47] where approximate circuits that exhibit dynamic accuracy reconfiguration are proposed. However, all these works are operation specific and they induce significant overheads at the accurate operation.…”

Section: Introductionmentioning

confidence: 99%

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Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

2020

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Leveraging the inherent error tolerance of a vast number of application domains that are rapidly growing, approximate computing arises as a design alternative to improve the efficiency of our computing systems by trading accuracy for energy savings. However, the requirement for computational accuracy is not fixed. Controlling the applied level of approximation dynamically at runtime is a key to effectively optimize energy, while still containing and bounding the induced errors at runtime. In this paper, we propose and implement an automatic and circuit independent design framework that generates approximate circuits with dynamically reconfigurable accuracy at runtime. The generated circuits feature varying accuracy levels, supporting also accurate execution. Extensive experimental evaluation, using industry strength flow and circuits, demonstrates that our generated approximate circuits improve the energy by up to 41% for 2% error bound and by 17.5% on average under a pessimistic scenario that assumes full accuracy requirement in the 33% of the runtime. To demonstrate further the efficiency of our framework, we considered two state-of-the-art technology libraries which are a 7nm conventional FinFET and an emerging technology that boosts performance at a high cost of increased dynamic power. INDEX TERMS Approximate computing, approximate design automation, dynamically reconfigurable accuracy, low power.

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“…Besides that, an easy way to design low power multiplier architecture is by creating power efficient full adder design in the adder tree. Approximate addition is another way to reduce the computational complexity [3]. Furthermore, the reduction of the power in adders is also possible through various bypassing designs where the number of zeros is more in the operands.…”

Section: Introductionmentioning

confidence: 99%

Design of Bit Slice Processor based on Reconfigurable Approximate Carry Look-Ahead Adder

2019

IJITEE

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A highly efficient approximate addition plays a vital role in arithmetic operations. A special addition mechanism employed in the proposed work consists of both exact and approximate modes of operation suitable for both error tolerant and exact applications. The proposed adder is more area and power efficient compared with other conventional approximate carry look-ahead adders. It is constructed by splitting the input into two parts namely, approximate part and augmenting part. If both produce carry it will be exact output, while the carry produced by approximate part will be imprecise. Based on this mechanism an efficient reconfigurable carry look-ahead adder is designed and applied to a bit-slice processor. Bit slicing is technique to construct a processor by using n-bit CPU. The error rate is also minimized in the proposed technique by 10% compared to existing designs. Compared with conventional approximate adder, the proposed reconfigurable approximate adder produce better results in terms of area and power

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Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Cited by 66 publications

References 17 publications

Hardware Optimized and Error Reduced Approximate Adder

Hardware Optimized and Error Reduced Approximate Adder

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

Design of Bit Slice Processor based on Reconfigurable Approximate Carry Look-Ahead Adder

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