Hardware Optimized and Error Reduced Approximate Adder

Abstract

This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)-and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.2 of 15 predominant on approximate logic circuits [12] and approximate arithmetic circuits such as adders and multipliers [13]. Here, the focus is on the design of an approximate adder.Many approximate adders in the existing literature are suited for an application specific integrated circuit (ASIC)-style implementation and only some are suitable for both ASIC-and field programmable gate array (FPGA)-based implementations. Hence, it is unlikely that many approximate adders in the literature, when implemented on an FPGA, would surpass a native accurate FPGA adder of similar size because an FPGA embeds accurate arithmetic units, such as adders and multipliers, which are highly optimized for speed and area.This paper proposes a new approximate adder that is suitable for FPGA-and ASIC-based implementations, and our focus is on a comparison with other approximate adders, which are also suited for FPGA-and ASIC-based implementations. The remainder of this paper is organized as follows. A survey of some popular existing literature on approximate adders is presented in Section 2. Following this, we present the proposed approximate adder (HOERAA) in Section 3. FPGA-based implementation results corresponding to accurate and approximate adders for 32-bit and 64-bit additi...

Design and Analysis of an Approximate Adder with Hybrid Error Reduction

“…For fair comparison, identical design parameters, i.e., n = 16 and k = 8, and the RCA structure were used for all the approximate adders. Furthermore, the bit-width of the constant part of the OLOCA and HOERAA were selected to be 6 [16,31].…”

“…In other words, only a few of the upper (n−k) LSB outputs are generated by the OR operation, and the remaining lower bits of the LSB outputs are fixed to "1." The hardware optimized error reduced adder (HOERRA) proposed by Balasubramanian et al [31] is another optimized version of the LOA, which is suitable for both field programmable gate array and application specific integrated circuit-based implementations. The approximate adder part of the HOERAA is similar to that of the OLOCA in that the (n−k−2) LSB outputs are set to "1."…”

Approximate CPU Design for IoT End-Devices with Learning Capabilities

“…Approximation at circuit level for adders covers a general implementation flow, which is generating larger approximate blocks by using smaller exact or inexact sub-adders. In [19], 8-bit approximate sub-adders are reconfigured to create 32-bit, 64-bit more efficient approximate designs in terms of critical path delay, area and power consumption. In [20], fixed sub-adders are used to create a reconfigurable generic adder structure.…”

An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

“…A number of approximate adders have been presented in the literature corresponding to an ASIC type implementation at the transistor and gate levels, and a pure FPGA based implementation. To mention some examples, [14,15] present transistor level approximate adders, [16][17][18][19][20] describe gate level approximate adders, and [21,22] discuss FPGA based approximate adders. In this work, we consider static approximation adders which are suitable for both an ASIC type implementation at the gate level and a FPGA based implementation.…”