Influences of low-temperature postdeposition annealing on memory properties of Al/Al2O3/Al-rich Al-O/SiO2/p-Si charge trapping flash memory structures

Ozaki, Shinya; Kato, Takashi; Kawae, Takeshi; Morimoto, Akira

doi:10.1116/1.4876135

Cited by 8 publications

(6 citation statements)

References 27 publications

(20 reference statements)

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“…In fact, by considering the difference in capacitance and therefore in equivalent oxide thickness (EOT) for memory wi th various CTLs, ZnO/NiO CTL remains the one with the largest memory window under the same electric field, manifesting the advantages of using ZnO/NiO over single ZnO and singe NiO as CTL. In fact, memory with ZnO/NiO CTL demonstrates a memory window of ~ 2 V by a small sweeping voltage of ±3 V which is much lower than those with CTLs of nanocrystals (NCs) such as Au NCs [32], HfAlO NCs [33], GaAs NCs [34] and Ti-Al-O NCs [35] and high-k dielectric such as HfO2 [36] and AlOx [37] to achieve comparable memory window. The mechanism behind the different memory window for three kinds of CTLs in the study can be understood by the band diagram for ZnO/NiO CTL with positive and negative gate bias shown in Fig.…”

Section: Trapping Layermentioning

confidence: 97%

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Chen

Teng

Chang

et al. 2016

IEEE J. Electron Devices Soc.

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Journal of the Electron Devices Society 6 V. CONCLUSION With incumbent flash memory devices operated in the range of 15-17 V, it is imperative to pursue green flash memory that can be operated at voltage less than 10 V to realize a sustainable environment. In this paper, two promising CTL types based on crystalline oxide including crystalline high-k dielectric and crystalline oxide semiconductor which possess the capability to achieve this goal are reviewed. For CTL based on crystalline high-k dielectric, the distinct advantage for memory operation is the k value higher than 30 which is much higher than the amorphous counterpart and beneficial to reduce operation voltage since a higher effective electric field can be exerted on the tunnel SiO2 due to electric flux density continuity. The most concerned retention issue of adopting a crystalline high-k CTL has also be circumvented by passivation of grain boundaries related defects through plasma treatment. The concept of employing crystalline high-k dielectric as CTL not only works for Si-channel flash memory but also Ge-channel memory devices which enable superior memory performance to Si-based counterpart due to higher carrier mobility and more desirable band structure. For CTL based on crystalline oxide semiconductor, a CTL formed by stacking n-type and p-type oxide semiconductor demonstrates typical diode characteristics with a built-in internal electric field. It is the unique internal field that enhances P/E speed while reducing the operation voltage. Both kinds of CTL create a differentiating and pioneering technology that gains an outlook on realizing green flash memory devices.

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Section: Trapping Layermentioning

confidence: 97%

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Chen

Teng

Chang

et al. 2016

IEEE J. Electron Devices Soc.

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“…The International Technology Roadmap for Semiconductors (ITRS) scaling projection for floating-gate NOR and NAND flash is shown comprehensively in the following tables ( Table 1 and Table 2 ). Nowadays, high -k dielectrics [ 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 ] are highly considered and widely implemented for CTM upon continually scaling down of the dimensions of flash memory [ 33 ]. The advantage of using high -k dielectrics is that for the same equivalent oxide thickness (EOT), the high -k dielectrics can have a thicker physical thickness than silicon dioxides.…”

Section: Introductionmentioning

confidence: 99%

Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm

et al. 2014

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Flash memory is the most widely used non-volatile memory device nowadays. In order to keep up with the demand for increased memory capacities, flash memory has been continuously scaled to smaller and smaller dimensions. The main benefits of down-scaling cell size and increasing integration are that they enable lower manufacturing cost as well as higher performance. Charge trapping memory is regarded as one of the most promising flash memory technologies as further down-scaling continues. In addition, more and more exploration is investigated with high-k dielectrics implemented in the charge trapping memory. The paper reviews the advanced research status concerning charge trapping memory with high-k dielectrics for the performance improvement. Application of high-k dielectric as charge trapping layer, blocking layer, and tunneling layer is comprehensively discussed accordingly.

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“…The hysteresis memory window increases from 0.26 and 0.52 V to 1.12 V for devices with NiO, ZnO, and ZnO/NiO chargetrapping layers, respectively. For devices with a ZnO/NiO charge-trapping layer, as shown in the figure, the window further enlarges to 2.02 V as the sweeping voltage increases to ±3 V. It is worth mentioning that, even with a conventional SiO 2 tunnel/blocking oxide, which has a relatively low κ value, under similar or even smaller ranges of sweeping voltage, the ZnO/NiO charge-trapping layer reveals the largest hysteresis memory window compared to other charge-trapping layers such as Au NCs, 1 graphene, 15 ZnO, 16,18 HfAlO NCs, 23 HfO 2 , 24 Si 3 N 4 , 24 Al-rich AlO x , 25 GaAs NCs, 26 and Ti−Al−O NCs, 27 where high-κ dielectrics were adopted as the tunnel/blocking oxide in most cases, and a comparison of the hysteresis memory windows among various charge-trapping layers is summarized in Table 1. The results indicate that the ZnO/NiO chargetrapping layer holds great potential to realize memory function with low operation voltage.…”

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confidence: 99%

ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation

Sun

Chen

Chu

et al. 2015

ACS Appl. Mater. Interfaces

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A stacked oxide semiconductor of n-type ZnO/p-type NiO with diode behavior was proposed as the novel charge-trapping layer to enable low-voltage flash memory for green electronics. The memory performance outperforms that of other devices with high κ and a nanocrystal-based charge-trapping layer in terms of a large hysteresis memory window of 2.02 V with ±3 V program/erase voltage, a high operation speed of 1.88 V threshold voltage shift by erasing at -4 V for 1 ms, negligible memory window degradation up to 10(5) operation cycles, and 16.2% charge loss after 10 years of operation at 85 °C. The promising electrical characteristics can be explained by the negative conduction band offset with respect to Si of ZnO that is beneficial to electron injection and storage, the large number of trapping sites of NiO that act as other good storage media, and most importantly the built-in electric field between n-type ZnO and p-type NiO that provides a favorable electric field for program and erase operation. The process of diode-based flash memory is fully compatible with incumbent VLSI technology, and utilization of the built-in electric field ushers in a new avenue of accomplishing green flash memory.

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Influences of low-temperature postdeposition annealing on memory properties of Al/Al2O3/Al-rich Al-O/SiO2/p-Si charge trapping flash memory structures

Cited by 8 publications

References 27 publications

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm

ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation

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