Influences of increasing gate stem height on DC and RF performances of InAlAs/InGaAs InP-based HEMTs*

Abstract

The T-gate stem height of InAlAs/InGaAs InP-based high electron mobility transistor (HEMT) is increased from 165 nm to 250 nm. The influences of increasing the gate stem height on the direct current (DC) and radio frequency (RF) performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage (V th) of 60 mV than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length, which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the InGaAs channel so that the transconductance (g m) of the high gate stem device is 70 mS/mm larger than that of the short stem device. As for the RF performances, the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum f t of 270 GHz and f max of 460 GHz, while the short gate stem device has a maximum f t of 240 GHz and the f max of 370 GHz.

Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs

“…From bottom to top, the layers consist of a 500-nm In 0.52 Al 0.48 As buffer layer, 10-nm ln 0.53 Ga 0.47 As channel layer, 3-nm unstrained ln 0.52 Al 0.48 As spacer layer, Si delta doping layer with 5 × 10 The fabrication process of InP HEMTs mainly contains six steps, including mesa isolation, Ohmic contact formation, gate-recess, T-gates, passivation, and connection pads, which is similar to our previous reported devices. [12,13] Firstly, isolating mesa was formed by means of phosphorus acid-based wet chemical etching. Next, source and drain were spaced 2.4 µm through a lithography process, followed by Ti/Pt/Au (15/15/50 nm) evaporated to satisfy the requirement of Ohmic contact by electron beam evaporation without annealing, with contact resistance measured to be 0.023 Ω•mm and the specific contact resistivity 8.75 × 10 −8 Ω•cm 2 by TLM method.…”

“…12 cm −2 doping concentration, 8-nm unstrained ln 0.52 Al 0.48 As Schot-tky barrier layer, 4-nm InP etch-stop layer and Si-doped In 0.65 Ga 0.35 As/In 0.53 Ga 0.47 As/ln 0.52 Al 0.48 As (10/15/15 nm) composite capping layers. Hall measurements were made at room temperature, showing a carrier mobility of over 12000 cm 2 /(V•s).…”

Impact of gate offset in gate recess on DC and RF performance of InAlAs/InGaAs InP-based HEMTs

“…The fabrication process of InP-based HEMTs consisted of four main steps, namely mesa isolation, Ohmic contact formation, gate recess, and T-shaped gate process, which was similar to our previously reported devices. [14] At first isolated mesa was formed to define the area of a device by means of phosphorus acid based wet chemical etching down to buffer layer. Then source and drain were defined by lithography with a 2.4-µm space in between.…”

“…f T was obtained by extrapolating H 21 curve to unit gain by a slope of −20 dB/decade. Moreover, due to the noisy characteristics of unilateral gain (U) which indicated insufficient estimation of f max variation, MAG/MSG was used to extrapolate f max , [13][14][15][16] as is shown in Fig. 5.…”

Effect of InxAl1-xAs graded buffer materials on pseudomorphic InP HEMT

“…From the material perspective, the most effective and the simplest way to improve the performance of HEMT materials is to increase the channel indium components. Because its results in reduced the width of the band gap and enhanced mobility of electrons in the channel (Takahashi et al, 2008;Ajayan and Nirmal, 2015;Shi et al, 2015;Tong et al, 2020;Zhong et al, 2020;Feng et al, 2022). However, the lattice mismatch between the pseudomorphic In y Ga 1-y As channel and the InAlAs buffer will occur.…”