Abstract:The concept of noise margin is crucial in the design and operation of digital logic circuits. Analytical expressions for the transfer curves of an inverter based on two depletion-mode p-type organic thin-film transistors (OTFTs) were calculated. Based on these expressions, the values for the noise margin of organic-based inverters were calculated. In this paper, the influence of the OTFT parameters on the noise margin is presented. Knowing that statistical variations of the transistor parameters are inherent t… Show more
“…If we neglect hard faults, to ensure robust circuit functionality and, hence, effective yield, the noise margin of each gate must be above a certain minimum value. 4,5 The threshold voltage has a very strong influence on the noise margin of an organic inverter. 4 For a given gate oxidesemiconductor system, the threshold voltage is normally fixed.…”
mentioning
confidence: 99%
“…4,5 The threshold voltage has a very strong influence on the noise margin of an organic inverter. 4 For a given gate oxidesemiconductor system, the threshold voltage is normally fixed. To independently tune the threshold voltage, we apply a second gate.…”
Increasing the noise margin in organic circuits using dual gate field-effect transistors Spijkman, M.; Smits, E. C. P.; Blom, P. W. M.; de Leeuw, D. M.; Saint Come, Y. Bon; Setayesh, S.; Cantatore, E.; Bon Saint Côme, Y.
“…If we neglect hard faults, to ensure robust circuit functionality and, hence, effective yield, the noise margin of each gate must be above a certain minimum value. 4,5 The threshold voltage has a very strong influence on the noise margin of an organic inverter. 4 For a given gate oxidesemiconductor system, the threshold voltage is normally fixed.…”
mentioning
confidence: 99%
“…4,5 The threshold voltage has a very strong influence on the noise margin of an organic inverter. 4 For a given gate oxidesemiconductor system, the threshold voltage is normally fixed. To independently tune the threshold voltage, we apply a second gate.…”
Increasing the noise margin in organic circuits using dual gate field-effect transistors Spijkman, M.; Smits, E. C. P.; Blom, P. W. M.; de Leeuw, D. M.; Saint Come, Y. Bon; Setayesh, S.; Cantatore, E.; Bon Saint Côme, Y.
“…However, for TFT technologies in amorphous silicon, organic and metal oxide semiconductors, it is difficult to find n-type/p-type semiconductor materials with the equivalent performance and compatible processes to build high performance complementary logic circuits. Consequently, various unipolar logic designs have been studied for implementation of TFT circuits, including diode-load [7], zero-V GS -load [8], dual-V th and pseudo-CMOS [9], which are based on p-type TFTs. Among them, the zero-V GS -load logic has been popularly used for its circuit simplicity, and relatively high noise margin (NM).…”
Abstract-The noise margin (NM) of an inverter is an important feature for the operation stability of the digital circuits. Owing to their simple structure, easy processes and relatively high gain, the unipolar zero-V GS -load logic design has been widely used for implementation of digital circuits in various thin-film transistor (TFT) technologies. In this work, a simple noise margin model clarifying the relationship between the NM and electrical/device parameters was developed for the zero-V GS -load inverter. The model was verified by circuit simulations, and is capable of providing a useful guideline for optimal design of unipolar TFT logic circuits. Finally, the application of the derived model in a static random access memory (SRAM) cell design was discussed.Index Terms-Noise margin, thin-film transistor, zero-V GS load inverter
“…Several research groups recently published alternative routes to decrease the cross-linking temperature. [13][14][15][16][17] The short curing time and low thermal budget requirement is still an important issue for the PVP film cross-linking process.…”
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