Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

Cui, Qingyu; Si, Mengwei; Sporea, Radu A.; Guo, Xiaojun

doi:10.1109/ted.2013.2251346

Cited by 13 publications

(8 citation statements)

References 8 publications

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“…4(a)). More interestingly, although (10) and (12) were derived based on a constant mobility, the calculated results can also have good fitting with the simulation results for the OTFT technology with a gate voltage dependent mobility as shown in Fig. 4(b).…”

Section: Resultsmentioning

confidence: 61%

“…V in,a approximately equals to V in,b [10]. For the unipolar logics, during the whole operation period, V out cannot be completely pulled up to V DD or down to the ground (GND).…”

Section: Derivation Of the Models (A)mentioning

confidence: 99%

“…t p can be described as t p = (t pLH + t pHL )/2, where t pLH is defined as the time it takes V out to charge from V min to (V min +V max )/2, and t pHL is defined as the time it takes the V out to discharge from V max to (V min +V max )/2. Based on (5), (6), (10) and (12), the expressions for t pLH and t pHL can be derived as: The average power consumption (P avg ) during a switching event in a logic circuit is composed of the static part (P stat ) and the dynamic part (P dyn ). In the p-type unipolar circuit, P stat is mainly contributed by the DC current from V DD to GND when V out is held high, since when V out is low, T D is slightly switched off with much lower leakage current as illustrated in Fig.…”

Section: Derivation Of the Models (A)mentioning

confidence: 99%

“…8, it can be seen that the increase of N and W D (layout area) can not only reduce the delay, but also increase the power consumption. To evaluate the power-delay tradeoffs in logic circuit design, the power-delay product (PDP) is introduced, standing for the average energy consumed per switching event, and is expressed as [10] is also added in Fig. 9(a) to show the design tradeoffs.…”

Section: Power-delay Product (Pdp)mentioning

confidence: 99%

“…Therefore, various unipolar logic designs have been proposed [17]- [19]. At present, noise margin analytical models have been developed for optimal design of TFT circuits for the required robustness and yield [10], [11], however, a study of delay and power trade-offs and development of related models has not yet been undertaken. In this work, transient models for delay and power analysis were developed for the zero-V GS load inverter, which is suitable for depletion-type TFTs to achieve high gain and large noise margin [20], [21].…”

mentioning

confidence: 99%

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Analytical Models for Delay and Power Analysis of Zero-V_GSLoad Unipolar Thin-Film Transistor Logic Circuits

Cui

Sporea

Liu

et al. 2014

IEEE Trans. Electron Devices

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Abstract-In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero-V GS -load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this work, the analytical models for delay and power were developed for zero-V GS -load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero-V GS -load logic circuits. Index Terms-delay, power, thin-film transistor, zero-V GS load inverter I. INTRODUCTIONITH the advances of various semiconductor materials including organic small molecules, polymers and metal oxides, and related processing techniques, the potential applications of thin-film transistors (TFTs) in general signal processing for ubiquitous electronics are attracting more and more attention [1]- [7]. To prompt these advanced TFT applications, circuit-level design and optimization is becoming as crucial as performance improvement at the material and device levels. Propagation delay and power dissipation are two key constraints to be concerned in optimal circuit design and synthesis [8], [9]. To analyze and extract the delay and power of complex circuits, development of analytical models for the basic inverter circuit is the first step [10]- [13]. In silicon, numerous delay and power analytical models have been proposed for the complementary inverter circuit [14]- [16].

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Section: Resultsmentioning

confidence: 61%

“…V in,a approximately equals to V in,b [10]. For the unipolar logics, during the whole operation period, V out cannot be completely pulled up to V DD or down to the ground (GND).…”

Section: Derivation Of the Models (A)mentioning

confidence: 99%

Section: Derivation Of the Models (A)mentioning

confidence: 99%

Section: Power-delay Product (Pdp)mentioning

confidence: 99%

mentioning

confidence: 99%

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Analytical Models for Delay and Power Analysis of Zero-V_GSLoad Unipolar Thin-Film Transistor Logic Circuits

Cui

Sporea

Liu

et al. 2014

IEEE Trans. Electron Devices

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Oxide TFTs on Flexible Substrates for Designing and Fabricating Analog-to-Digital Converters

Correia¹,

Goes²,

Barquinha³

2016

Technological Innovation for Cyber-Physical Systems

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Thin-film transistors (TFTs) employing oxide semiconductors have recently emerged in electronics, offering excellent performance and stability, low processing temperature and large area processing, being indium-galliumzinc oxide (IGZO) the most popular amorphous oxide semiconductor. In this work it is shown how IGZO TFTs can be integrated with multilayer high-κ dielectrics to obtain low operating voltages, both on glass and flexible PEN substrates. Then, the electrical properties extracted from these devices are used to design and simulate a 2 nd-order Sigma-Delta (∑∆) analog-to-digital converter (ADC), showing superior performance (e.g. SNDR≈57 dB, and DR≈65 dB) over ADCs using competing thin-film technologies.

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Multi-Functional Molybdenum Oxide Doping to Improve the Electrical Characteristics of Indium Oxide Thin Film Transistors

Heo,

Lee,

Tarsoly

et al. 2024

Electron. Mater. Lett.

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Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

Cited by 13 publications

References 8 publications

Analytical Models for Delay and Power Analysis of Zero-V_GSLoad Unipolar Thin-Film Transistor Logic Circuits

Analytical Models for Delay and Power Analysis of Zero-V_GSLoad Unipolar Thin-Film Transistor Logic Circuits

Oxide TFTs on Flexible Substrates for Designing and Fabricating Analog-to-Digital Converters

Multi-Functional Molybdenum Oxide Doping to Improve the Electrical Characteristics of Indium Oxide Thin Film Transistors

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Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

Cited by 13 publications

References 8 publications

Analytical Models for Delay and Power Analysis of Zero-VGSLoad Unipolar Thin-Film Transistor Logic Circuits

Analytical Models for Delay and Power Analysis of Zero-VGSLoad Unipolar Thin-Film Transistor Logic Circuits

Oxide TFTs on Flexible Substrates for Designing and Fabricating Analog-to-Digital Converters

Multi-Functional Molybdenum Oxide Doping to Improve the Electrical Characteristics of Indium Oxide Thin Film Transistors

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Product

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Analytical Models for Delay and Power Analysis of Zero-V_GSLoad Unipolar Thin-Film Transistor Logic Circuits

Analytical Models for Delay and Power Analysis of Zero-V_GSLoad Unipolar Thin-Film Transistor Logic Circuits