Analytical Models for Delay and Power Analysis of Zero-V_GSLoad Unipolar Thin-Film Transistor Logic Circuits

Abstract

Abstract-In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero-V GS -load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this work, the analytical models for delay and power were developed for zero-V GS -load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero-V GS -load logic circuits. Index Terms-delay, power, thin-film transistor, zero-V GS load inverter I. INTRODUCTIONITH the advances of various semiconductor materials including organic small molecules, polymers and metal oxides, and related processing techniques, the potential applications of thin-film transistors (TFTs) in general signal processing for ubiquitous electronics are attracting more and more attention [1]- [7]. To prompt these advanced TFT applications, circuit-level design and optimization is becoming as crucial as performance improvement at the material and device levels. Propagation delay and power dissipation are two key constraints to be concerned in optimal circuit design and synthesis [8], [9]. To analyze and extract the delay and power of complex circuits, development of analytical models for the basic inverter circuit is the first step [10]- [13]. In silicon, numerous delay and power analytical models have been proposed for the complementary inverter circuit [14]- [16].