Influence of device engineering on the analog and RF performances of SOI MOSFETs

Kilchytska, Valeriya; Nève, Amaury; Vancaillie, Laurent; Levacq, David; Adriaensen, Stéphane; Meer, H. van; Meyer, K. De; Raynaud, C.; Dehan, M.; Raskin, Jean‐Pierre; Flandre, Denis

doi:10.1109/ted.2003.810471

Cited by 219 publications

(94 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Thus, the optimization of the SDE region is extremely important to minimize C gg associated with structure. It is important to note that such a drastic reduction in parasitic capacitance is not possible in other approaches [4], [5] that have been suggested for improving analog FOM. Fig.…”

Section: Resultsmentioning

confidence: 99%

“…However, in the nanoscale regime, upcoming CMOS technologies face many technological challenges [1], the most crucial being the SCEs that tend to degrade the analog figures of merit (FOM) such as Early voltage (V EA ), transconductance-to-current ratio (g m /I ds ), intrinsic dc gain (A VO = g m /g ds = g m /I ds × V EA ) and cutoff frequency (f T = g m /2πC gg where g m is the transconductance and C gg is the total gate capacitance) [2], [3]. To overcome the degradation in analog FOM, certain techniques such as HALO implants and laterally asymmetric channel (LAC) or graded-channel (GC) design [4], [5] have been proposed. However, in nanoscale devices, the control of the dopant profile at the source end of the channel (enabling a feasible LAC/GC or HALO concept) is a technological challenge.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

Kranti

Armstrong

2007

IEEE Trans. Electron Devices

105

View full text Add to dashboard Cite

Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

Kranti

Armstrong

2007

IEEE Trans. Electron Devices

105

View full text Add to dashboard Cite

“…The important characteristics for the design of analog integrated circuit are drain current (I d ), trans-conductance (g m ), output conductance (g d ), dc intrinsic gain (A v ), early voltage (V EA ), trans-conductance-to-drain current ratio otherwise known as trans-conductance generation factor (TGF), cut off frequency (f T ) [27].…”

Section: Analog and High Frequency Performancementioning

confidence: 99%

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

Sahu¹,

Mohapatra²,

Pradhan³

2013

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

show abstract

“…The key figures of merit which characterize the analog performance of a MOSFET are the output conductance (g d ), transconductance (g m ), intrinsic gain (g m /g d ) and the transconductance generation factor (g m /I D ) of the device [20,21]. Further, the gate capacitance (C G ) which is normally defined as the sum of parasitic gate-to-source (C gs ) and gate-to-drain (C gd ) capacitances plays a vital role in analog circuits.…”

Section: Analog Performancementioning

confidence: 99%

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

Patil

Qureshi²

2012

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-In this paper, the impact of segregation layer density (N DSL ) and length (L DSL ) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the N DSL the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the L DSL the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a commonsource amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing N DSL and L DSL of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits

show abstract

Influence of device engineering on the analog and RF performances of SOI MOSFETs

Cited by 219 publications

References 25 publications

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

Contact Info

Product

Resources

About