Industrial Demands on Process and Device Simulation

Schwerin, A. v.; Spitzer, A.

doi:10.1007/978-3-7091-6827-1_87

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“…It is widely unders- tood that three-dimensional numerical calculation with a large simulation area requires a huge memory size and CPU time for the serial computational approach [4].…”

Section: B Topography Simulationmentioning

confidence: 99%

An extracting capacitance in a stacked DRAM cell by numerical method

Yoon

Kwon²,

Yoon³

et al.

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502)

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Abstruct -This paper reports a methodology and its application for extracting capacitance in a stacked DRAM cell structure by numerical technique. To calculate the cell and parasitic capacitance in a stacked DRAM cell, we employed finite element method (FEM) and to generate complicated three-dimensional mesh structure, we used a graphic user interface, a topography simulator and threedimensional grid generator. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 pm was chosen as a test vehicle to check the validity of the simulation. I n this work, 62 parasitic capacitance with 4 cell-capacitance were extracted from a stacked DRAM cell structure.

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“…It is widely unders- tood that three-dimensional numerical calculation with a large simulation area requires a huge memory size and CPU time for the serial computational approach [4].…”

Section: B Topography Simulationmentioning

confidence: 99%