An extracting capacitance in a stacked DRAM cell by numerical method

Abstract

Abstruct -This paper reports a methodology and its application for extracting capacitance in a stacked DRAM cell structure by numerical technique. To calculate the cell and parasitic capacitance in a stacked DRAM cell, we employed finite element method (FEM) and to generate complicated three-dimensional mesh structure, we used a graphic user interface, a topography simulator and threedimensional grid generator. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 pm was chosen as a test vehicle to check the validity of the simulation. I n this work, 62 parasitic capacitance with 4 cell-capacitance were extracted from a stacked DRAM cell structure.