Indium–Tin-Oxide Transistors with One Nanometer Thick Channel and Ferroelectric Gating

Abstract

In this work, we demonstrate high performance indium-tin-oxide (ITO) transistors with the channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. On-current of 0.243 A/mm is achieved on sub-micron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ω⋅mm and a low contact resistivity of 1.1×10 -7 Ω⋅cm 2 . The ITO transistor with a recessed channel and ferroelectric gating demonstrates several advantages over 2D semiconductor transistors and other thin film transistors, including large-area wafer-size nanometer thin film formation, low contact resistance and contact resistivity, atomic thin channel being immunity to short channel effects, large gate modulation of high carrier density by ferroelectric gating, high-quality gate dielectric and passivation formation, and a large bandgap for the low-power back-end-of-line (BEOL) CMOS application.

Hafnium–zirconium oxide interface models with a semiconductor and metal for ferroelectric devices

“…The DFT calculations suggesting the following should enhance the endurance: 1) suppressing the interlayer formation by employing a channel less prone to oxidation (e.g., Ge, SiGe or oxide semiconductors), 2) reduction of voltage drop in the DE layer either by employing interlayer materials with higher k value or 3) by lowering the operating voltage by using ferroelectric subloops to reduce the voltage drop in the DE layer. It is noted that there are several reports of enhanced endurance using oxide semiconductor channel in FeFETS[27][28][29][30] or Ge MOSCAPs 31 consistent with the above suggestions. Note that it is very difficult to quantitatively model any enhanced endurance since this requires a complicated set of kinetic Monte Carlo calculations.…”

Mapping the nanoscale effects of charge traps on electrical transport in grain structures of indium tin oxide thin films

“… 34–36 So, we calculated the trap density assuming an average carrier density which should be a good approximation. 37 Using this equation, we calculated the effective charge trap density ( N eff ) map of an ITO thin film ( Fig. 3b ), as well as S I / I 2 ( Fig.…”

“…3436 Please do not adjust margins Please do not adjust margins approximation. 37 Using this equation, we calculated the effective charge trap density (N eff ) map of an ITO thin film from (Fig. 3b), S I /I 2 (Fig.…”

A Fully Integrated Ferroelectric Thin‐Film‐Transistor – Influence of Device Scaling on Threshold Voltage Compensation in Displays

“…FE‐TFTs have been fabricated and discussed so far as artificial synapse, [ 17 ] back end of line TFT, [ 18 ] and non‐volatile memory. [ 19,20 ] For an effective compensation of the aforementioned device‐to‐device variabilities, an accurate control of the polarization state and analog/linear switching between multiple intermediate states is necessary.…”