Increased hole trapping in gate oxides as latent damage from plasma charging

Abstract

With aggressive device scaling and the wide use of plasma-assisted processes, the device damage caused by process-induced charging is receiving growing attention, from both basic understanding and technological points of view. The paper presents results of hole-trapping studies in the thin gate oxide of plasma-damaged NMOS and PMOS transistors. In addition to neutral electron traps and passivated interface damage, which are commonly observed in plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. Enhanced hole trapping in the gate oxide of plasma-damaged devices was studied using Fowler-Nordheim stress and substrate hot-hole injection applied to antenna test structures sensitive to process-induced charging. The number of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole-trap generation is based on electrical stress and current flow, forced through the oxide due to charging under plasma etching or ion implantation conditions.

Statistical Characterization of Process-Induced Plasma Damage

“…This means that increasing either parameter results in a decrease in V T . The negative V T shift is consistent with other antenna-MOSFET data [7]. The observed V T shift is closely related to the increase in the plasma nonuniformity stated earlier.…”

“…Antenna-embedded MOS transistors were used to study charging damage [6][7][8]. A variety of charging damage models were reported to understand the mechanisms.…”

Effect of source and drain junctions on plasma charging

“…We believe this mechanism confirms the injection type in the centre region as well as in the perimeter region and makes the device independent of damage during gate injection in an NMOS transistor. The V t in the lower IETS region is higher for the gate injection region showing a larger positive-charge build up during gate injection as hole trapping is relatively suppressed during positive gate bias (substrate injection) [5]. This result further supports the idea that the current injection direction during this plasma charging experiment changed signs, from the centre (substrate injection) to the edge of the wafer (gate injection).…”

“…Note that it is normal for n-channel V t to decrease with increasing damage [4]. Since we expect the centre region to experience substrate injection during plasma charging, the damage induced electron traps are dominant contributors to the net charge in the oxide [5]. The V t in the perimeter region, however, initially starts to decrease and later becomes independent of IETS.…”

Plasma-Induced Damage on the Performance and Reliability of Low-Temperature Polycrystalline Silicon Thin-Film Transistors

“…When the plasma nonuniformity is sufficiently large and the electric field across the gate oxide exceeds a critical value, electron injects through the gate oxide via Fowler-Nordheim tunneling, causing deterioration of the oxide quality and integrity. 8 The injection process could occur through either substrate injection or gate injection, depending upon the potential distribution at the wafer surface during the plasma process. 9 Moreover, the degree of plasma damage is strongly related to the topography of the gate interconnect.…”